Why on-chip cache coherence is here to stay

Published

Journal Article

The article discusses how on-chip hardware coherence can scale gracefully as the number of cores increases. Cache coherence has come to dominate the market for technical, as well as for legacy, reasons. Technically, hardware cache coherence provides performance generally superior to what is achievable with software-implemented coherence. Coherence's alleged lack of scalability arises from claims of unscalable storage and interconnection network traffic and concerns over latency and energy. Before investigating the issues involved in coherence's future, one first needs to describe today's cache coherence protocols. When a core issues a load or store that misses in its private cache, it issues a coherence request message to the shared cache. Based on the block's coherence state and per-core tracking bits, the shared cache either responds directly or forwards the request to the one or more cores that need to respond to the request.

Full Text

Duke Authors

Cited Authors

  • Martin, MMK; Hill, MD; Sorin, DJ

Published Date

  • July 1, 2012

Published In

Volume / Issue

  • 55 / 7

Start / End Page

  • 78 - 89

Electronic International Standard Serial Number (EISSN)

  • 1557-7317

International Standard Serial Number (ISSN)

  • 0001-0782

Digital Object Identifier (DOI)

  • 10.1145/2209249.2209269

Citation Source

  • Scopus