Architectures for online error detection and recovery in multicore processors

Published

Journal Article

The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies will become more vulnerable to: (a) environmental disturbances that produce transient (or soft) errors, (b) latent manufacturing defects as well as aging/wearout phenomena that produce permanent (or hard) errors, and (c) verification inefficiencies that allow important design bugs to escape in the system. In an effort to cope with these reliability threats, several research teams have recently proposed multicore processor architectures that provide low-cost dependability guarantees against hardware errors and design bugs. This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation. It discusses taxonomy of representative approaches and presents a qualitative comparison based on: hardware cost, performance overhead, types of faults detected, and detection latency. It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging methodology. © 2011 EDAA.

Duke Authors

Cited Authors

  • Gizopoulos, D; Psarakis, M; Adve, SV; Ramachandran, P; Hari, SKS; Sorin, D; Meixner, A; Biswas, A; Vera, X

Published Date

  • May 31, 2011

Published In

Start / End Page

  • 533 - 538

International Standard Serial Number (ISSN)

  • 1530-1591

Citation Source

  • Scopus