An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2
Journal Article
Recently, several researchers have proposed schemes for low-cost, low-power error detection in the processor core. In this work, we demonstrate that one particular scheme, an enhanced implementation of the Argus framework called Argus-2, is a viable option for industry adoption. Using an FPGA prototype, we experimentally evaluate Argus-2′s ability to detect errors due to (a) all possible single stuck-at faults in a given core and (b) a statistically significant number of double stuck-at faults, including pairs of faults that are randomly located and pairs that are spatially correlated on the chip.
Full Text
Duke Authors
Cited Authors
- Eibl, PJ; Meixner, A; Sorin, DJ
Published Date
- July 15, 2011
Published In
Volume / Issue
- 39 / 1 SPEC. ISSUE
Start / End Page
- 121 - 122
International Standard Serial Number (ISSN)
- 0163-5999
Digital Object Identifier (DOI)
- 10.1145/2007116.2007131
Citation Source
- Scopus