Reduced precision checking for a floating point adder
Publication
, Journal Article
Eibl, PJ; Cook, AD; Sorin, DJ
Published in: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
December 1, 2009
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. Our analysis establishes a relationship between the width of the checker adder's mantissa and the worst-case magnitude of an undetected error in the primary adder result. This relationship allows for a tradeoff between error detection capability and area overhead that is not offered by any previously developed floating point adder checking schemes. Experimental results of fault injection experiments are presented which support our analysis. © 2009 IEEE.
Duke Scholars
Published In
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOI
ISSN
1550-5774
Publication Date
December 1, 2009
Start / End Page
145 / 152
Citation
APA
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Eibl, P. J., Cook, A. D., & Sorin, D. J. (2009). Reduced precision checking for a floating point adder. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 145–152. https://doi.org/10.1109/DFT.2009.22
Eibl, P. J., A. D. Cook, and D. J. Sorin. “Reduced precision checking for a floating point adder.” Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, December 1, 2009, 145–52. https://doi.org/10.1109/DFT.2009.22.
Eibl PJ, Cook AD, Sorin DJ. Reduced precision checking for a floating point adder. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2009 Dec 1;145–52.
Eibl, P. J., et al. “Reduced precision checking for a floating point adder.” Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Dec. 2009, pp. 145–52. Scopus, doi:10.1109/DFT.2009.22.
Eibl PJ, Cook AD, Sorin DJ. Reduced precision checking for a floating point adder. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2009 Dec 1;145–152.
Published In
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOI
ISSN
1550-5774
Publication Date
December 1, 2009
Start / End Page
145 / 152