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Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures

Publication ,  Journal Article
Meixner, A; Sorin, DJ
Published in: IEEE Transactions on Dependable and Secure Computing
January 1, 2009

Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. Correct operation of the memory system is defined by the memory consistency model. Errors can therefore be detected by checking if the observed memory system behavior deviates from the specified consistency model. Based on recent work, we design a framework for dynamic verification of memory consistency (DVMC). The framework consists of mechanisms to verify three invariants that are proven to guarantee that a specified memory consistency model is obeyed. We describe an implementation of the framework for the SPARCv9 architecture, and we experimentally evaluate its performance using full-system simulation of commercial workloads. © 2006 IEEE.

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Published In

IEEE Transactions on Dependable and Secure Computing

DOI

ISSN

1545-5971

Publication Date

January 1, 2009

Volume

6

Issue

1

Start / End Page

18 / 31

Related Subject Headings

  • Strategic, Defence & Security Studies
  • 4606 Distributed computing and systems software
  • 4604 Cybersecurity and privacy
  • 0805 Distributed Computing
  • 0804 Data Format
  • 0803 Computer Software
 

Citation

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Meixner, A., & Sorin, D. J. (2009). Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Transactions on Dependable and Secure Computing, 6(1), 18–31. https://doi.org/10.1109/TDSC.2007.70243
Meixner, A., and D. J. Sorin. “Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures.” IEEE Transactions on Dependable and Secure Computing 6, no. 1 (January 1, 2009): 18–31. https://doi.org/10.1109/TDSC.2007.70243.
Meixner A, Sorin DJ. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Transactions on Dependable and Secure Computing. 2009 Jan 1;6(1):18–31.
Meixner, A., and D. J. Sorin. “Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures.” IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 1, Jan. 2009, pp. 18–31. Scopus, doi:10.1109/TDSC.2007.70243.
Meixner A, Sorin DJ. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Transactions on Dependable and Secure Computing. 2009 Jan 1;6(1):18–31.

Published In

IEEE Transactions on Dependable and Secure Computing

DOI

ISSN

1545-5971

Publication Date

January 1, 2009

Volume

6

Issue

1

Start / End Page

18 / 31

Related Subject Headings

  • Strategic, Defence & Security Studies
  • 4606 Distributed computing and systems software
  • 4604 Cybersecurity and privacy
  • 0805 Distributed Computing
  • 0804 Data Format
  • 0803 Computer Software