Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults
Publication
, Journal Article
Romanescu, BF; Sorin, DJ
Published in: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
December 1, 2008
To improve the lifetime performance of a multicore chip with simple cores, we propose the Core Cannibalization Architecture (CCA). A chip with CCA provisions a fraction of the cores as cannibalizable cores (CCs). In the absence of hard faults, the CCs function just like normal cores. In the presence of hard faults, the CCs can be cannibalized for spare parts at the granularity of pipeline stages. We have designed and laid out CCA chips composed of multiple OpenRISC 1200 cores. Our results show that CCA improves the chips' lifetime performances, compared to chips without CCA. Copyright 2008 ACM.
Duke Scholars
Published In
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
DOI
ISSN
1089-795X
Publication Date
December 1, 2008
Start / End Page
43 / 51
Citation
APA
Chicago
ICMJE
MLA
NLM
Romanescu, B. F., & Sorin, D. J. (2008). Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 43–51. https://doi.org/10.1145/1454115.1454124
Romanescu, B. F., and D. J. Sorin. “Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults.” Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, December 1, 2008, 43–51. https://doi.org/10.1145/1454115.1454124.
Romanescu BF, Sorin DJ. Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2008 Dec 1;43–51.
Romanescu, B. F., and D. J. Sorin. “Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults.” Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, Dec. 2008, pp. 43–51. Scopus, doi:10.1145/1454115.1454124.
Romanescu BF, Sorin DJ. Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2008 Dec 1;43–51.
Published In
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
DOI
ISSN
1089-795X
Publication Date
December 1, 2008
Start / End Page
43 / 51