Self-checking and self-diagnosing 32-bit microprocessor multiplier

Published

Journal Article

In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P). Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty subunit off-line. We utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Our analysis shows that our scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads. © 2006 IEEE.

Full Text

Duke Authors

Cited Authors

  • Yilmaz, M; Hower, DR; Ozev, S; Sorin, DJ

Published Date

  • January 1, 2006

Published In

International Standard Serial Number (ISSN)

  • 1089-3539

Digital Object Identifier (DOI)

  • 10.1109/TEST.2006.297634

Citation Source

  • Scopus