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Tolerating hard faults in microprocessor array structures

Publication ,  Journal Article
Bower, FA; Shealy, PG; Ozev, S; Sorin, DJ
Published in: Proceedings of the International Conference on Dependable Systems and Networks
January 1, 2004

In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row." We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.

Duke Scholars

Published In

Proceedings of the International Conference on Dependable Systems and Networks

DOI

Publication Date

January 1, 2004

Start / End Page

51 / 60
 

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Bower, F. A., Shealy, P. G., Ozev, S., & Sorin, D. J. (2004). Tolerating hard faults in microprocessor array structures. Proceedings of the International Conference on Dependable Systems and Networks, 51–60. https://doi.org/10.1109/dsn.2004.1311876
Bower, F. A., P. G. Shealy, S. Ozev, and D. J. Sorin. “Tolerating hard faults in microprocessor array structures.” Proceedings of the International Conference on Dependable Systems and Networks, January 1, 2004, 51–60. https://doi.org/10.1109/dsn.2004.1311876.
Bower FA, Shealy PG, Ozev S, Sorin DJ. Tolerating hard faults in microprocessor array structures. Proceedings of the International Conference on Dependable Systems and Networks. 2004 Jan 1;51–60.
Bower, F. A., et al. “Tolerating hard faults in microprocessor array structures.” Proceedings of the International Conference on Dependable Systems and Networks, Jan. 2004, pp. 51–60. Scopus, doi:10.1109/dsn.2004.1311876.
Bower FA, Shealy PG, Ozev S, Sorin DJ. Tolerating hard faults in microprocessor array structures. Proceedings of the International Conference on Dependable Systems and Networks. 2004 Jan 1;51–60.

Published In

Proceedings of the International Conference on Dependable Systems and Networks

DOI

Publication Date

January 1, 2004

Start / End Page

51 / 60