Automated optimization of look-up table implementation for function evaluation on FPGAs

Published

Journal Article

This paper presents a systematic approach for automatic generation of look-up-table (LUT) for function evaluations and minimization in hardware resource on field programmable gate arrays (FPGAs). The class of functions supported by this approach includes sine, cosine, exponentials, Gaussians, the central B-splines, and certain cylinder functions that are frequently used in applications for signal and image processing and data processing. In order to meet customer requirements in accuracy and speed as well as constraints on the use of area and on-chip memory, the function evaluation is based on numerical approximation with Taylor polynomials. Customized data precisions are supported in both fixed point and floating point representations. The optimization procedure involves a search in three-dimensional design space of data precision, sampling density and approximation degree. It utilizes both model-based estimates and gradient-based information gathered during the search. The approach was tested with actual synthesis results on the Xilinx Virtex-2Pro FPGA platform. © 2009 SPIE.

Full Text

Duke Authors

Cited Authors

  • Deng, L; Chakrabarti, C; Pitsianis, N; Sun, X

Published Date

  • November 11, 2009

Published In

Volume / Issue

  • 7444 /

International Standard Serial Number (ISSN)

  • 0277-786X

Digital Object Identifier (DOI)

  • 10.1117/12.834184

Citation Source

  • Scopus