Geometric tiling for reducing power consumption in structured matrix operations


Journal Article

This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving. © 2006 IEEE.

Full Text

Duke Authors

Cited Authors

  • Chen, G; Xue, L; Kim, J; Sobti, K; Deng, L; Sun, X; Pitsianis, N; Chakrabarti, C; Kandemir, M; Vijaykrishnan, N

Published Date

  • December 1, 2007

Published In

  • 2006 Ieee International Systems on Chip Conference, Soc

Start / End Page

  • 113 - 114

Digital Object Identifier (DOI)

  • 10.1109/SOCC.2006.283861

Citation Source

  • Scopus