A dynamic programming solution for optimizing test delivery in multicore SOCs

Conference Paper

We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization. Test-time minimization for grid-based NOCs is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. The proposed method yields high-quality results that are comparable to integer linear programming (ILP), but unlike ILP, it is scalable to large SOCs with many cores. We present results on synthetic NOC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores. © 2012 IEEE.

Full Text

Duke Authors

Cited Authors

  • Agrawal, M; Richter, M; Chakrabarty, K

Published Date

  • December 1, 2012

Published In

International Standard Serial Number (ISSN)

  • 1089-3539

International Standard Book Number 13 (ISBN-13)

  • 9781467315951

Digital Object Identifier (DOI)

  • 10.1109/TEST.2012.6401535

Citation Source

  • Scopus