High density packaging in 2010 and beyond
As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2003 with 100 nm features, pitch of area array I/Os of the nano ICs will move towards 20-100 micron. Increasing system functionality and system-on-a-chip will place demands on the package to support extremely high digital clock speeds beyond 5 GHz, RF signals to 40 GHz, and optical data rates beyond 100 Gbps all on a single, highly integrated package or board. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends both in IC and systems packaging including SIP, wafer level packaging are steps in the right direction, but represent partial system solutions. The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board. This paper reviews systems, IC, and high density packaging trends and summarizes the latest PRC developments in high density SOP packaging technology.
Tummala, RR; Sundaram, V; Liu, F; White, G; Hattacharya, S; Pulugurtha, RM; Swaminathan, M; Dalmia, S; Laskar, J; Jokerst, NM; Chow, SY
Proceedings of the 4th International Symposium on Electronic Materials and Packaging, Emap 2002
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International Standard Book Number 10 (ISBN-10)
International Standard Book Number 13 (ISBN-13)
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