SNDR sensitivity analysis for cascaded ΣΔ modulators
Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics will be characterized.
Morizio, J; Hoke, M; Kocak, T; Geddie, C; Hughes, C; Perry, J; Madhavapeddi, S; Hood, M; Huffman, W; Okuda, T; Noda, H; Morimoto, Y; Kumamoto, T; Ishiwaki, M; Kondoh, H
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