Disintegrated control for energy-efficient and heterogeneous memory systems

Journal Article

A mix of emerging technologies promises qualitatively new memory system capabilities. However, today's memory controllers and channels constrain heterogeneity. Today's integration of controllers on processor dies prevents systems from accommodating diverse, technology-specific protocols and schedulers in a modular manner; memory design decisions must be made during processor design. Moreover, today's channel architectures are not flexible enough to accommodate diverse demands for bandwidth and capacity. To address these challenges, we present strategies for scalability and heterogeneity, which include (i) disintegrating memory controllers to support heterogeneous command protocols in a modular manner; (ii) adding buffers to ensure signal integrity; and (iii) organizing buffers hierarchically to reduce latency. We apply these strategies to architect a novel heterogeneous DRAM / PCM system. Finally, we present mechanisms for power-efficient data movement. © 2013 IEEE.

Full Text

Duke Authors

Cited Authors

  • Ham, TJ; Chelepalli, BK; Xue, N; Lee, BC

Published Date

  • 2013

Published In

Start / End Page

  • 424 - 435

International Standard Serial Number (ISSN)

  • 1530-0897

Digital Object Identifier (DOI)

  • 10.1109/HPCA.2013.6522338