Exploring memory consistency for massively-threaded throughput-oriented processors

Published

Journal Article

We re-visit the issue of hardware consistency models in the new context of massively-threaded throughput-oriented processors (MTTOPs). A prominent example of an MTTOP is a GPGPU, but other examples include Intel's MIC architecture and some recent academic designs. MTTOPs differ from CPUs in many significant ways, including their ability to tolerate latency, their memory system organization, and the characteristics of the software they run. We compare implementations of various hardware consistency models for MTTOPs in terms of performance, energy-efficiency, hardware complexity, and programmability. Our results show that the choice of hardware consistency model has a surprisingly minimal impact on performance and thus the decision should be based on hardware complexity, energy-efficiency, and programmability. For many MTTOPs, it is likely that even a simple implementation of sequential consistency is attractive. Copyright 2013 ACM.

Full Text

Duke Authors

Cited Authors

  • Hechtman, BA; Sorin, DJ

Published Date

  • August 12, 2013

Published In

Start / End Page

  • 201 - 212

International Standard Serial Number (ISSN)

  • 1063-6897

Digital Object Identifier (DOI)

  • 10.1145/2485922.2485940

Citation Source

  • Scopus