Skip to main content

Current scaling in aligned carbon nanotube array transistors with local bottom gating

Publication ,  Journal Article
Franklin, AD; Lin, A; Wong, HSP; Chen, Z
Published in: IEEE Electron Device Letters
July 1, 2010

A local-bottom-gate (LBG) configuration is introduced for carbon nanotube array field-effect transistors (FETs) (CNTFETs). CNTFETs from highly aligned nanotubes are demonstrated and exhibit the best performance to date, with current density >40μA/μm (with no metallic nanotubes), inverse subthreshold slope of 70 mV/decade, and on/off-current ratio >105. Additionally, on-current from LBG-CNTFETs is shown to scale linearly with the number of nanotube channels. These advancements in device geometry and performance provide a new platform for further progress to be made toward high-performance FETs from aligned nanotubes. © 2010 IEEE.

Duke Scholars

Altmetric Attention Stats
Dimensions Citation Stats

Published In

IEEE Electron Device Letters

DOI

ISSN

0741-3106

Publication Date

July 1, 2010

Volume

31

Issue

7

Start / End Page

644 / 646

Related Subject Headings

  • Applied Physics
  • 4009 Electronics, sensors and digital hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Franklin, A. D., Lin, A., Wong, H. S. P., & Chen, Z. (2010). Current scaling in aligned carbon nanotube array transistors with local bottom gating. IEEE Electron Device Letters, 31(7), 644–646. https://doi.org/10.1109/LED.2010.2047231
Franklin, A. D., A. Lin, H. S. P. Wong, and Z. Chen. “Current scaling in aligned carbon nanotube array transistors with local bottom gating.” IEEE Electron Device Letters 31, no. 7 (July 1, 2010): 644–46. https://doi.org/10.1109/LED.2010.2047231.
Franklin AD, Lin A, Wong HSP, Chen Z. Current scaling in aligned carbon nanotube array transistors with local bottom gating. IEEE Electron Device Letters. 2010 Jul 1;31(7):644–6.
Franklin, A. D., et al. “Current scaling in aligned carbon nanotube array transistors with local bottom gating.” IEEE Electron Device Letters, vol. 31, no. 7, July 2010, pp. 644–46. Scopus, doi:10.1109/LED.2010.2047231.
Franklin AD, Lin A, Wong HSP, Chen Z. Current scaling in aligned carbon nanotube array transistors with local bottom gating. IEEE Electron Device Letters. 2010 Jul 1;31(7):644–646.

Published In

IEEE Electron Device Letters

DOI

ISSN

0741-3106

Publication Date

July 1, 2010

Volume

31

Issue

7

Start / End Page

644 / 646

Related Subject Headings

  • Applied Physics
  • 4009 Electronics, sensors and digital hardware
  • 0906 Electrical and Electronic Engineering