Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors
Single-walled carbon nanotubes (CNTs) offer attractive performance benefits as the channel material for aggressively scaled digital transistors that operate at low voltages. Progress continues to be made resolving the materials challenges of CNT purification and placement [1]. Meanwhile, a better understanding of the origin and role of contact resistance in scaled CNT field-effect transistors (CNTFETs) is a key device-level area that requires further study. Scalability of the CNTFET channel has already been shown to sub-10 nm [2], yielding ballistic transport and device performance that is limited entirely by the contacts. Future technology nodes (e.g., 7 nm, 5 nm, etc.) will not only require scaled channels, but also comparably scaled contact lengths to the sub-15 nm regime. All of the FET options for future technologies suffer from high contact resistance as contact length (Lc) is scaled down. To reach the targeted device-level contact resistance (Rc-DEV) of 100-150 Ω•μm, the contact resistance for a specific device structure must first be properly defined. In this work, we define the relevant aspects of a CNTFET contact and the corresponding resistances, putting them into the proper context for a sub-10 nm technology node. Also, new results on the use of different metal-CNT contacts and how they impact the Rc vs. Lc scaling is presented. © 2014 IEEE.
