Combined hierarchical placement algorithm for row-based layouts
Publication
, Journal Article
Kim, C; Kim, W; Shin, H; Rhee, K; Chung, H; Kim, J
Published in: Electronics Letters
January 1, 1993
A hierarchical placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimise the number of crossing nets, while the objective of placement by simulated annealing is usually to minimise the total estimated wire length. The combined placement algorithm can optimise both the routing density and the estimated wire length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction. Several standard-cell and sea-of-gates (SOG) circuits are placed using this algorithm and promising results are obtained. © 1993, The Institution of Electrical Engineers. All rights reserved.
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Published In
Electronics Letters
DOI
ISSN
0013-5194
Publication Date
January 1, 1993
Volume
29
Issue
17
Start / End Page
1508 / 1510
Related Subject Headings
- Electrical & Electronic Engineering
- 1005 Communications Technologies
- 0906 Electrical and Electronic Engineering
- 0801 Artificial Intelligence and Image Processing
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Kim, C., Kim, W., Shin, H., Rhee, K., Chung, H., & Kim, J. (1993). Combined hierarchical placement algorithm for row-based layouts. Electronics Letters, 29(17), 1508–1510. https://doi.org/10.1049/el:19931005
Kim, C., W. Kim, H. Shin, K. Rhee, H. Chung, and J. Kim. “Combined hierarchical placement algorithm for row-based layouts.” Electronics Letters 29, no. 17 (January 1, 1993): 1508–10. https://doi.org/10.1049/el:19931005.
Kim C, Kim W, Shin H, Rhee K, Chung H, Kim J. Combined hierarchical placement algorithm for row-based layouts. Electronics Letters. 1993 Jan 1;29(17):1508–10.
Kim, C., et al. “Combined hierarchical placement algorithm for row-based layouts.” Electronics Letters, vol. 29, no. 17, Jan. 1993, pp. 1508–10. Scopus, doi:10.1049/el:19931005.
Kim C, Kim W, Shin H, Rhee K, Chung H, Kim J. Combined hierarchical placement algorithm for row-based layouts. Electronics Letters. 1993 Jan 1;29(17):1508–1510.
Published In
Electronics Letters
DOI
ISSN
0013-5194
Publication Date
January 1, 1993
Volume
29
Issue
17
Start / End Page
1508 / 1510
Related Subject Headings
- Electrical & Electronic Engineering
- 1005 Communications Technologies
- 0906 Electrical and Electronic Engineering
- 0801 Artificial Intelligence and Image Processing