Processing techniques for vertical interconnects
Processing techniques that address the interconnect issues required for fabrication of deep sub-micron electronic devices and for three-dimensional (3D) integration of these components will be described. As the interconnect density increases, alternate methods of providing input/output (I/O) leads on a chip are required. One attractive approach to providing increased connectivity is to use through-wafer interconnects. This reduces the interconnect density on the front surface while providing additional I/Os on the back surface. It also provides a convenient mechanism for integrating two or more die to form a 3D integrated structure. Processing techniques under development include: high aspect ratio silicon etching, insulator lining, adhesion/barrier layer deposition, seed layer deposition, electroplating, and chemical mechanical planarization (CMP).
