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FPGA Accelerated INDEL realignment in the cloud

Publication ,  Conference
Wu, L; Bruns-Smith, D; Nothaft, FA; Huang, Q; Karandikar, S; Le, J; Lin, A; Mao, H; Sweeney, B; Asanovic, K; Patterson, DA; Joseph, AD
Published in: Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019
March 26, 2019

The amount of data being generated in genomics is predicted to be between 2 and 40 exabytes per year for the next decade, making genomic analysis the new frontier and the new challenge for precision medicine. This paper explores targeted deployment of hardware accelerators in the cloud to improve the runtime and throughput of immensescale genomic data analyses. In particular, INDEL (INsertion/DELetion) realignment is a critical operation that enables diagnostic testings of cancer through error correction prior to variant calling. It is the slowest part of the somatic (cancer) genomic analysis pipeline, the alignment refinement pipeline, and represents roughly one-third of the execution time of timesensitive diagnostics for acute cancer patients. To accelerate genomic analysis, this paper describes a hardware accelerator for INDEL realignment (IR), and a hardware-software framework leveraging FPGAs-as-a-service in the cloud. We chose to implement genomics analytics on FPGAs because genomic algorithms are still rapidly evolving (e.g. the de facto standard "GATK Best Practices" has had five releases since January of this year). We chose to deploy genomics accelerators in the cloud to reduce capital expenditure and to provide a more quantitative performance and cost analysis. We built and deployed a sea of IR accelerators using our hardware-software accelerator development framework on AWS EC2 F1 instances. We show that our IR accelerator system performed 81× better than multi-threaded genomic analysis software while being 32× more cost efficient.

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Published In

Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019

DOI

ISBN

9781728114446

Publication Date

March 26, 2019

Start / End Page

277 / 290
 

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Wu, L., Bruns-Smith, D., Nothaft, F. A., Huang, Q., Karandikar, S., Le, J., … Joseph, A. D. (2019). FPGA Accelerated INDEL realignment in the cloud. In Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019 (pp. 277–290). https://doi.org/10.1109/HPCA.2019.00044
Wu, L., D. Bruns-Smith, F. A. Nothaft, Q. Huang, S. Karandikar, J. Le, A. Lin, et al. “FPGA Accelerated INDEL realignment in the cloud.” In Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, 277–90, 2019. https://doi.org/10.1109/HPCA.2019.00044.
Wu L, Bruns-Smith D, Nothaft FA, Huang Q, Karandikar S, Le J, et al. FPGA Accelerated INDEL realignment in the cloud. In: Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. 2019. p. 277–90.
Wu, L., et al. “FPGA Accelerated INDEL realignment in the cloud.” Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, 2019, pp. 277–90. Scopus, doi:10.1109/HPCA.2019.00044.
Wu L, Bruns-Smith D, Nothaft FA, Huang Q, Karandikar S, Le J, Lin A, Mao H, Sweeney B, Asanovic K, Patterson DA, Joseph AD. FPGA Accelerated INDEL realignment in the cloud. Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. 2019. p. 277–290.

Published In

Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019

DOI

ISBN

9781728114446

Publication Date

March 26, 2019

Start / End Page

277 / 290