Skip to main content

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation.

Publication ,  Journal Article
Liu, J; Brooke, MA; Hirotsu, K
Published in: IEEE transactions on neural networks
January 2002

The paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm: the random weight change (RWC) algorithm. The algorithm does not require a known desired neural network output for error calculation and is suitable for direct feedback control. With hardware experiments, we demonstrate that the RWC chip, as a direct feedback controller, successfully suppresses unstable oscillations modeling combustion engine instability in real time.

Duke Scholars

Published In

IEEE transactions on neural networks

DOI

EISSN

1941-0093

ISSN

1045-9227

Publication Date

January 2002

Volume

13

Issue

5

Start / End Page

1178 / 1186

Related Subject Headings

  • Artificial Intelligence & Image Processing
  • 4602 Artificial intelligence
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Liu, J., Brooke, M. A., & Hirotsu, K. (2002). A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation. IEEE Transactions on Neural Networks, 13(5), 1178–1186. https://doi.org/10.1109/tnn.2002.1031948
Liu, J., M. A. Brooke, and K. Hirotsu. “A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation.IEEE Transactions on Neural Networks 13, no. 5 (January 2002): 1178–86. https://doi.org/10.1109/tnn.2002.1031948.
Liu J, Brooke MA, Hirotsu K. A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation. IEEE transactions on neural networks. 2002 Jan;13(5):1178–86.
Liu, J., et al. “A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation.IEEE Transactions on Neural Networks, vol. 13, no. 5, Jan. 2002, pp. 1178–86. Epmc, doi:10.1109/tnn.2002.1031948.
Liu J, Brooke MA, Hirotsu K. A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation. IEEE transactions on neural networks. 2002 Jan;13(5):1178–1186.

Published In

IEEE transactions on neural networks

DOI

EISSN

1941-0093

ISSN

1045-9227

Publication Date

January 2002

Volume

13

Issue

5

Start / End Page

1178 / 1186

Related Subject Headings

  • Artificial Intelligence & Image Processing
  • 4602 Artificial intelligence