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Load latency tolerance in dynamically scheduled processors

Publication ,  Conference
Srinivasan, ST; Lebeck, AR
Published in: Proceedings of the Annual International Symposium on Microarchitecture
December 1, 1998

This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our simulations use flexible load completion policies instead of a fixed memory hierarchy that dictates the latency. Although our policies delay load completion as long as possible, they produce performance (instructions committed per cycle (IPC)) comparable to an ideal memory system where all loads complete in one cycle. Our measurements reveal that to produce IPC values within 8% of the ideal memory system, between 1% and 62% of loads need to be satisfied within a single cycle and that up to 84% can be satisfied in as many as 32 cycles, depending on the benchmark and processor configuration. Load latency tolerance is largely determined by whether an unpredictable branch is in the load's data dependence graph and the depth of the dependence graph. Our results also show that up to 36% of all loads miss in the level one cache yet have latency demands lower than second level cache access times. We also show that up to 37% of loads hit in the level one cache even though they possess enough latency tolerance to be satisfied by lower levels of the memory hierarchy.

Duke Scholars

Published In

Proceedings of the Annual International Symposium on Microarchitecture

ISSN

1072-4451

Publication Date

December 1, 1998

Start / End Page

148 / 159
 

Citation

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Srinivasan, S. T., & Lebeck, A. R. (1998). Load latency tolerance in dynamically scheduled processors. In Proceedings of the Annual International Symposium on Microarchitecture (pp. 148–159).
Srinivasan, S. T., and A. R. Lebeck. “Load latency tolerance in dynamically scheduled processors.” In Proceedings of the Annual International Symposium on Microarchitecture, 148–59, 1998.
Srinivasan ST, Lebeck AR. Load latency tolerance in dynamically scheduled processors. In: Proceedings of the Annual International Symposium on Microarchitecture. 1998. p. 148–59.
Srinivasan, S. T., and A. R. Lebeck. “Load latency tolerance in dynamically scheduled processors.” Proceedings of the Annual International Symposium on Microarchitecture, 1998, pp. 148–59.
Srinivasan ST, Lebeck AR. Load latency tolerance in dynamically scheduled processors. Proceedings of the Annual International Symposium on Microarchitecture. 1998. p. 148–159.

Published In

Proceedings of the Annual International Symposium on Microarchitecture

ISSN

1072-4451

Publication Date

December 1, 1998

Start / End Page

148 / 159