Geometric tiling for reducing power consumption in structured matrix operations
Publication
, Journal Article
Chen, G; Xue, L; Kim, J; Sobti, K; Deng, L; Sun, X; Pitsianis, N; Chakrabarti, C; Kandemir, M; Vijaykrishnan, N
Published in: 2006 IEEE International Systems-on-Chip Conference, SOC
January 1, 2006
This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving. © 2006 IEEE.
Duke Scholars
Published In
2006 IEEE International Systems-on-Chip Conference, SOC
DOI
Publication Date
January 1, 2006
Start / End Page
113 / 114
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Chen, G., Xue, L., Kim, J., Sobti, K., Deng, L., Sun, X., … Vijaykrishnan, N. (2006). Geometric tiling for reducing power consumption in structured matrix operations. 2006 IEEE International Systems-on-Chip Conference, SOC, 113–114. https://doi.org/10.1109/SOCC.2006.283861
Chen, G., L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, and N. Vijaykrishnan. “Geometric tiling for reducing power consumption in structured matrix operations.” 2006 IEEE International Systems-on-Chip Conference, SOC, January 1, 2006, 113–14. https://doi.org/10.1109/SOCC.2006.283861.
Chen G, Xue L, Kim J, Sobti K, Deng L, Sun X, et al. Geometric tiling for reducing power consumption in structured matrix operations. 2006 IEEE International Systems-on-Chip Conference, SOC. 2006 Jan 1;113–4.
Chen, G., et al. “Geometric tiling for reducing power consumption in structured matrix operations.” 2006 IEEE International Systems-on-Chip Conference, SOC, Jan. 2006, pp. 113–14. Scopus, doi:10.1109/SOCC.2006.283861.
Chen G, Xue L, Kim J, Sobti K, Deng L, Sun X, Pitsianis N, Chakrabarti C, Kandemir M, Vijaykrishnan N. Geometric tiling for reducing power consumption in structured matrix operations. 2006 IEEE International Systems-on-Chip Conference, SOC. 2006 Jan 1;113–114.
Published In
2006 IEEE International Systems-on-Chip Conference, SOC
DOI
Publication Date
January 1, 2006
Start / End Page
113 / 114