Scholars@Duke
Lisa Wills

Lisa Wills

Assistant Professor of Computer Science
Computer Science
D304 LSRC, 308 Research Drive, Durham, NC 27708
D304 LSRC, 308 Research Drive, Durham, NC 27708

Scholarly Works - Journal articles

BigLittleMCA: A Spatially-Optimal Tiled Hardware Accelerator for MCMC Image Processing

Journal article ACM Transactions on Architecture and Code Optimization · September 17, 2025 Markov-Chain Monte-Carlo (MCMC) algorithms offer a general framework for performing interpretable inference but have high overheads due to the computational complexity of the sampling process and the large number of samples required to produce an accurate ... Full text Cite

Transferable Presynthesis PPA Estimation for RTL Designs with Data Augmentation Techniques

Journal article IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems · January 1, 2025 In modern VLSI design flow, evaluating the quality of register-transfer level (RTL) designs involves time-consuming logic synthesis using electronic design automation tools, a process that often slows down early optimization. While recent machine learning ... Full text Cite

Message from Program Chairs

Journal article Proceedings 2024 IEEE International Symposium on Workload Characterization Iiswc 2024 · January 1, 2024 Full text Cite

Accelerating Genomic Data Analytics with Composable Hardware Acceleration Framework

Journal article IEEE Micro · May 1, 2021 This article presents a framework, Genesis (genome analysis), to efficiently and flexibly accelerate generic data manipulation operations that have become performance bottlenecks in the genomic data processing pipeline utilizing FPGAs-as-a-service. Genesis ... Full text Cite

The Q100 Database Processing Unit

Journal article IEEE Micro · May 1, 2015 The Q100 uses hardware specialization to improve the energy efficiency of analytic database applications. The proposed accelerators are called database processing units. DPUs are analogous to GPUs, but where GPUs target graphics applications, DPUs target a ... Full text Cite

Energy analysis of hardware and software range partitioning

Journal article ACM Transactions on Computer Systems · September 23, 2014 Data partitioning is a critical operation for manipulating large datasets because it subdivides tasks into pieces that are more amenable to efficient processing. It is often the limiting factor in database performance and represents a significant fraction ... Full text Cite

Hardware partitioning for big data analytics

Journal article IEEE Micro · January 1, 2014 Targeted deployment of hardware accelerators can improve the throughput and energy efficiency of large-scale data processing. Data partitioning is a critical operation for manipulating large datasets and is often the limiting factor in database performance ... Full text Cite

Cache impacts of datatype acceleration

Journal article IEEE Computer Architecture Letters · January 1, 2012 Hardware acceleration is a widely accepted solution for performance and energy efficient computation because it removes unnecessary hardware for general computation while delivering exceptional performance via specialized control paths and execution units. ... Full text Cite

CryptoManiac: A fast flexible architecture for secure communication

Journal article Conference Proceedings Annual International Symposium on Computer Architecture ISCA · January 1, 2001 The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will be further underscored with the widespread adoption ... Full text Cite