ConferenceIEEE International Symposium on Performance Analysis of Systems and Software Ispass · January 1, 2025
Hardware Development is challenging in large part due to the complexity of incorporating realistic designs onto hardware devices (e.g., FPGAs, CGRAs, ASICs). This work proposes a multi-core, hardware-software accelerator design framework called Beethoven. ...
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ConferenceProceedings of the 20th Usenix Symposium on Networked Systems Design and Implementation Nsdi 2023 · January 1, 2023
Recent years have witnessed the wide adoption of RDMA in the cloud to accelerate first-party workloads and achieve cost savings by freeing up CPU cycles. Now cloud providers are working towards supporting RDMA in general-purpose guest VMs to benefit third- ...
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ConferenceProceedings 2022 IEEE 36th International Parallel and Distributed Processing Symposium IPDPS 2022 · January 1, 2022
Many data-intensive applications, such as distributed deep learning and data analytics, require moving vast amounts of data between compute servers in a distributed system. To meet the demands of these applications, datacenters are adopting Remote Direct M ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · April 17, 2021
Statistical machine learning often uses probabilistic models and algorithms, such as Markov Chain Monte Carlo (MCMC), to solve a wide range of problems. Probabilistic computations, often considered too slow on conventional processors, can be accelerated wi ...
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ConferenceProceedings of the 14th Eurosys Conference 2019 · March 25, 2019
Distributed file systems often exhibit high tail latencies, especially in large-scale datacenters and in the presence of competing (and possibly higher priority) workloads. This paper introduces techniques for managing tail latencies in these systems, whil ...
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ConferenceLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics · January 1, 2019
Graphics Processing Units (GPUs) are energy-efficient massively parallel accelerators that are increasingly deployed in multi-tenant environments such as data-centers for general-purpose computing as well as graphics applications. Using GPUs in multi-tenan ...
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ConferenceProceedings International Symposium on Computer Architecture · July 19, 2018
The increasing difficulty in leveraging CMOS scaling for improved performance requires exploring alternative technologies. A promising technique is to exploit the physical properties of devices to specialize certain computations. A recently proposed approa ...
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ConferenceMobisys 2018 Proceedings of the 16th ACM International Conference on Mobile Systems Applications and Services · June 10, 2018
The most promising way to improve the performance of dynamic information-flow tracking (DIFT) for machine code is to only track instructions when they process tainted data. Unfortunately, prior approaches to on-demand DIFT are a poor match for modern mobil ...
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ConferenceProceedings 2016 43rd International Symposium on Computer Architecture ISCA 2016 · August 24, 2016
The increasing use of probabilistic algorithms from statistics and machine learning for data analytics presents new challenges and opportunities for the design of computing systems. One important class of probabilistic machine learning algorithms is Markov ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · January 1, 2014
Trends in increasing web traffic demand an increase in server throughput while preserving energy efficiency and total cost of ownership. Present work in optimizing data center efficiency primarily focuses on the data center as a whole, using off-the-shelf ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture Micro · December 1, 2010
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, the proposed family of cache coherence protocols can be formally verified cor ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · March 13, 2010
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framework for ...
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ConferenceProceedings International Symposium on High Performance Computer Architecture · January 1, 2010
We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction and data ...
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ConferenceACM SIGPLAN Notices · January 1, 2010
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framework for ...
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ConferenceProceedings International Conference on Computer Communications and Networks ICCCN · November 12, 2009
Shrinking CMOS feature sizes and the integration of novel nanotechnologies onto silicon platforms are both likely to increase fabrication defects. As a result, on-chip networks become more and more irregular due to defects and it becomes more challenging t ...
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ConferenceACM SIGPLAN Notices · January 1, 2009
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new computing domains and automate tasks that currently require expert scientific trai ...
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Conference2006 1st International Conference on Nano Networks and Workshops Nano Net · December 1, 2006
DNA-based self-assembly of nanoelectronic devices is an emerging technology that has the potential to enable terato peta-scale device integration. However, self-assembly currently is limited to manufacturing small computing blocks (nodes) which must then b ...
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Conference2nd Conference on Foundations of Nanoscience Self Assembled Architectures and Devices Fnano 2005 · December 1, 2005
We have designed and experimentally demonstrated the self-assembly of an addressable DNA lattice (i.e., a unique tile for each position in the lattice) using a two-step tile annealing procedure. Our method can be applied to a variety of systems including a ...
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ConferenceUsenix 2005 Annual Technical Conference · January 1, 2005
Deadlock can occur wherever multiple processes interact. Most existing static and dynamic deadlock detection tools focus on simple types of deadlock, such as those caused by incorrect ordering of lock acquisitions. In this paper, we propose Pulse, a novel ...
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Conference2004 IEEE International Symposium on Performance Analysis of Systems and Software · June 14, 2004
There is increasing concern among developers that future web servers running commercial workloads may be limited by network processing overhead in the CPU as 10Gb ethernet becomes prevalent. We analyze CPU usage of real hardware running popular commercial ...
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ConferenceAnnual ACM Symposium on Parallel Algorithms and Architectures · December 1, 2003
A model was created for determining criticality in MP systems. An algorithm was devised for computing criticality and criticality of real MP workloads was evaluated. A directed acyclic graph (DAG) model for executing: critical path and slack; mapping DAGs ...
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ConferenceAnnual ACM Symposium on Parallel Algorithms and Architectures · January 1, 2003
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed acyclic graph (DAG) model for characterizing program microexecutions on unip ...
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ConferenceLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics · January 1, 2003
Modern DRAM technologies offer power management features for optimization between performance and energy consumption. This paper employs Petri nets to model and evaluate memory controller policies for manipulating multiple power states. The model has been ...
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ConferenceProceedings International Parallel and Distributed Processing Symposium IPDPS 2003 · January 1, 2003
High performance, freedom from deadlocks, and freedom from livelocks are desirable properties of interconnection networks. Unfortunately, these can be conflicting goals because networks may either devote or under-utilize resources to avoid deadlocks and li ...
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ConferenceProceedings of the General Track 2003 Usenix Annual Technical Conference · January 1, 2003
The global nature of energy creates challenges and opportunities for developing operating system policies to effectively manage energy consumption in battery-powered mobile/wireless devices. The proposed currentcy model creates the framework for the operat ...
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ConferenceLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics · December 1, 2002
Prefetching is often used to overlap memory latency with computation for array-based applications. However, prefetching for pointer-intensive applications remains a challenge because of the irregular memory access pattern and pointer-chasing problem. In th ...
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ConferenceOperating Systems Review ACM · December 1, 2002
Energy consumption has recently been widely recognized as a major challenge of computer systems design. This paper explores how to support energy as a first-class operating system resource. Energy, because of its global system nature, presents challenges b ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · October 5, 2002
Energy consumption has recently been widely recognized as a major challenge of computer systems design. This paper explores how to support energy as a first-class operating system resource. Energy, because of its global system nature, presents challenges b ...
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ConferenceConference Proceedings Annual International Symposium on Computer Architecture ISCA · January 1, 2002
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately, naively scaling conventional window desi ...
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ConferenceSIGPLAN Notices ACM Special Interest Group on Programming Languages · January 1, 2001
We develop from first principles an exact model of the behavior of loop nests executing in a memory hierarchy, by using a nontraditional classification of misses that has the key property of composability. We use Presburger formulas to express various kind ...
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ConferenceProceedings of the International Symposium on Low Power Electronics and Design Digest of Technical Papers · January 1, 2001
The increasing importance of energy efficiency has produced a multitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an ...
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ConferenceConference Proceedings Annual International Symposium on Computer Architecture ISCA · January 1, 2001
Current memory hierarchies exploit locality of references to reduce load latency and thereby improve processor performance. Locality based schemes aim at reducing the number of cache misses and tend to ignore the nature of misses. This leads to a potential ...
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ConferenceIEEE High Performance Computer Architecture Symposium Proceedings · January 1, 2001
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point by reducing the load on the network. Congestion control via source throttlin ...
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ConferenceProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation PLDI · January 1, 2001
We develop from first principles an exact model of the behavior of loop nests executing in a memory hierarchy, by using a nontraditional classification of misses that has the key property of composability. We use Presburger formulas to express various kind ...
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ConferenceProceedings of the 9th Workshop on ACM Sigops European Workshop Beyond the PC New Challenges for the Operating System Ew 2000 · September 17, 2000
This paper advocates revisiting all aspects of Operating System design and implementation with energy-efficiency as the primary objective rather than the traditional OS metrics of maximizing performance and fairness. Energy is an increasingly important res ...
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ConferenceProceedings of the International Conference on Supercomputing · January 1, 2000
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetching can often overlap memory latency with computation for array-based numeric a ...
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ConferenceSIGPLAN Notices ACM Special Interest Group on Programming Languages · January 1, 2000
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory is a particularly important target for efforts to improve energy efficiency. ...
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ConferenceSIGCSE 1999 Proceedings of the 13th SIGCSE Technical Symposium on Computer Science Education · March 24, 1999
The wide-spread use of microprocessor based systems that utilize cache memory to alleviate excessively long DRAM access times introduces a new dimension in the quest to obtain good program performance. To fully exploit the performance potential of these fa ...
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ConferenceSIGCSE Bulletin Association for Computing Machinery Special Interest Group on Computer Science Education · January 1, 1999
The wide-spread use of microprocessor based systems that utilize cache memory to alleviate excessively long DRAM access times introduces a new dimension in the quest to obtain good program performance. To fully exploit the performance potential of these fa ...
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ConferenceAnnual ACM Symposium on Parallel Algorithms and Architectures · January 1, 1999
Matrix multiplication is an important kernel in linear algebra algorithms, and the performance of both serial and parallel implementations is highly dependent on the memory system behavior. Unfortunately, due to false sharing and cache conflicts, tradition ...
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ConferenceProceedings of the International Conference on Supercomputing · January 1, 1999
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory. This layout function is fixed at language definition time and constitutes an ...
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ConferenceLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics · January 1, 1999
As the importance of cache performance increases, allowing software to assist in cache management decisions becomes an attractive alternative. This paper focuses primarily on a mechanism for software to convey information to the memory hierarchy. We introd ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture · December 1, 1998
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture · December 1, 1998
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our simulations use flexible load completion policies instead of a fixed memory ...
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ConferenceProceedings of the International Conference on Supercomputing · November 7, 1998
Strassen's algorithm for matrix multiplication gains its lower arithmetic complexity at the expense of reduced locality of reference, which makes it challenging to implement the algorithm efficiently on a modern machine with a hierarchical memory system. W ...
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ConferenceIEEE International Symposium on High Performance Distributed Computing Proceedings · January 1, 1997
New network technology continues to improve both the latency and bandwidth of communication in computer clusters. The fastest high-speed networks approach or exceed the I/O bus bandwidths of 'gigabit-ready' hosts. These advances introduce new consideration ...
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ConferenceProceedings of the 1995 ACM Sigmetrics Joint International Conference on Measurement and Modeling of Computer Systems Sigmetrics 1995 Performance 1995 · May 1, 1995
This paper describes the active memory abstraction for memory-system simulation. In this abstraction-designed specifically for on-the-fly simulation, memory references logically invoke a user-specified function depending upon the reference's type and acces ...
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ConferenceACM SIGARCH (Association for Computing Nachinery Special Interest Group on Computer Architecture) - Conference Proceedings · January 1, 1995
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages by having a processor automatically invalidate its local copy of a cache blo ...
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ConferenceConference Proceedings Annual International Symposium on Computer Architecture ISCA · January 1, 1995
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages by having a processor automatically invalidate its local copy of a cache blo ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · November 1, 1994
This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache-coherent shared memory. This paper focu ...
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ConferenceProceedings of the ACM IEEE Supercomputing Conference · January 1, 1994
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented some or all of their cache coherence protocols in software. One way to exploit the flexibility of this software is to tailor a coherence protocol to match a ...
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ConferenceConference Proceedings Annual Symposium on Computer Architecture · January 1, 1993
This paper explores the complexity of implementing directory protocols by examining their mechanisms - primitive operations on directories, caches, and network interfaces. We compare the following protocols: Dir1B, Dir4B, Dir4
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