ConferenceProceedings International Symposium on Computer Architecture · January 1, 2024
We revisit the question of how many virtual networks (VNs) are required to provably avoid deadlock in a cache coherence protocol. The textbook way of reasoning about VNs says that the number of VNs depends on the longest chain of message dependencies in th ...
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ConferenceParallel Architectures and Compilation Techniques Conference Proceedings Pact · January 1, 2024
Designing a pipeline for a multicore processor is difficult. One major challenge is designing it such that the pipeline correctly enforces the intended memory consistency model (MCM). We have developed the PipeGen design automation tool to allow architects ...
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ConferenceProceedings of the 56th Annual IEEE ACM International Symposium on Microarchitecture Micro 2023 · October 28, 2023
Experiments with computer processors must account for the inherent variability in executions. Prior work has shown that real systems exhibit variability, and random effects must be injected into simulators to account for it. Thus, we can run multiple execu ...
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ConferenceProceedings International Symposium on High Performance Computer Architecture · January 1, 2022
We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we ...
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ConferenceProceedings 2022 IEEE International Symposium on Performance Analysis of Systems and Software Ispass 2022 · January 1, 2022
The deployment of increasingly large and capable FPGAs has motivated mechanisms for sharing them, but system support for FPGAs is not yet mature. Traditional scheduling algorithms do not account for the unique characteristics of FPGAs, leading to infeasibl ...
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ConferenceProceedings 2021 IEEE International Symposium on Performance Analysis of Systems and Software Ispass 2021 · March 1, 2021
Achieving peak performance on sparse operations is challenging. The distribution of the non-zero elements and underlying hardware platform affect the execution efficiency. Given the diversity in workloads and architectures, no unique solution always wins. ...
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ConferenceIEEE International Conference on Intelligent Robots and Systems · October 24, 2020
Precomputed roadmaps can enable effective multi-query motion planning: a roadmap can be built for a robot as if no obstacles were present, and then after edges invalidated by obstacles observed at query time are deleted, path search through the remaining r ...
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ConferenceProceedings 50th Annual IEEE IFIP International Conference on Dependable Systems and Networks Dsn 2020 · June 1, 2020
Racetrack memory is a promising new non-volatile memory technology, especially because of the density of its 3D implementation. However, for 3D racetrack to reach its potential, certain reliability issues must be overcome. Prior work used per-track encodin ...
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ConferenceProceedings International Symposium on Computer Architecture · May 1, 2020
We present HieraGen, a new tool for automatically generating hierarchical cache coherence protocols. HieraGen's inputs are the simple, atomic, stable state protocols for each level of the hierarchy. HieraGen's output is a highly concurrent hierarchical pro ...
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ConferenceProceedings of the 2020 Design Automation and Test in Europe Conference and Exhibition Date 2020 · March 1, 2020
Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabric ...
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ConferenceProceedings of the International Conference on Application Specific Systems Architectures and Processors · July 1, 2019
We have designed a programmable architecture to accelerate collision detection and graph search, two of the principal components of robotic motion planning. The programmability enables the architecture to be applied to a wide range of different robots and ...
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ConferenceProceedings 49th Annual IEEE IFIP International Conference on Dependable Systems and Networks Dsn 2019 · June 1, 2019
Racetrack memory is an exciting emerging memory technology with the potential to offer far greater capacity and performance than other non-volatile memories. Racetrack memory has an unusual error model, though, which precludes the use of the typical error ...
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ConferenceProceedings International Symposium on Computer Architecture · July 19, 2018
Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors. A coherence transaction comprises multiple messages, and these messages can interleave with other conflicting coheren ...
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ConferenceProceedings 35th IEEE International Conference on Computer Design Iccd 2017 · November 22, 2017
In this paper, we introduce Jenga, a new scheme for protecting 3D DRAM, specifically high bandwidth memory (HBM), from failures in bits, rows, banks, channels, dies, and TSVs. By providing redundancy at the granularity of a cache block rather than across b ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture Micro · October 14, 2017
Recent work in formal verification theory and verification-aware design has sought to bridge the divide between the class of protocols architects want to design and the class of protocols that are verifiable with state of the art tools. Particularly, the r ...
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ConferenceProceedings of the 16th Conference on Formal Methods in Computer Aided Design Fmcad 2016 · March 24, 2017
We present Neo, a framework for designing pre-verified protocol components that can be instantiated and connected in an arbitrarily large hierarchy (tree), with a guarantee that the whole system satisfies a given safety property. We employ the idea of netw ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture Micro · December 14, 2016
We have developed a hardware accelerator for motion planning, a critical operation in robotics. In this paper, we present the microarchitecture of our accelerator and describe a prototype implementation on an FPGA. We experimentally show that the accelerat ...
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ConferenceProceedings 46th Annual IEEE IFIP International Conference on Dependable Systems and Networks Dsn 2016 · September 29, 2016
Motivated by embedded systems and datacenters that require long-life components, we extend the lifetime of Flash memory using rewriting codes that allow for multiple writes to a page before it needs to be erased. Although researchers have previously explor ...
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ConferenceRobotics Science and Systems · January 1, 2016
We describe a process that constructs robot-specific circuitry for motion planning, capable of generating motion plans approximately three orders of magnitude faster than existing methods. Our method is based on building collision detection circuits for a ...
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ConferenceACM International Conference Proceeding Series · October 5, 2015
We integrate coding techniques and layout design to elimi- nate write-disturb in phase change memories (PCMs), while enhancing lifetime and host-visible capacity. We first pro- pose a checkerboard confguration for cell layout to elimi- nate write-disturb w ...
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ConferenceIspass 2015 IEEE International Symposium on Performance Analysis of Systems and Software · April 27, 2015
Although definition of single-program benchmarks is relatively straight-forward-a benchmark is a program plus a specific input-definition of multi-program benchmarks is more complex. Each program may have a different runtime and they may have different int ...
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ConferenceInternational Conference for High Performance Computing Networking Storage and Analysis Sc · January 16, 2014
In this work, we provide energy-efficient architectural support for floating point accuracy. For each floating point addition performed, we "recycle" that operation's rounding error. We make this error architecturally visible such that it can be used, when ...
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ConferenceProceedings Design Automation and Test in Europe Date · January 1, 2014
We propose a new, low-cost, hardware-only scheme to detect errors in superscalar, out-of-order processor cores. For each instruction decoded, Nostradamus compares what the instruction is expected to do against what the instruction actually does. We impleme ...
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ConferenceProceedings - International Symposium on High-Performance Computer Architecture · 2014
The goal of this work is to design cache coherence protocols with many cores that can be verified with state-of-the-art automated verification methodologies. In particular, we focus on flat (non-hierarchical) coherence protocols, and we use a mostly-automa ...
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ConferenceProceedings International Symposium on High Performance Computer Architecture · January 1, 2014
Dynamic power management (DPM) is critical to maximizing the performance of systems ranging from multicore processors to datacenters. However, one formidable challenge with DPM schemes is verifying that the DPM schemes are correct as the number of computat ...
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ConferenceInternational Multidisciplinary Scientific Geoconference Surveying Geology and Mining Ecology Management Sgem · December 1, 2013
At this moment the fly ash is deposed into huge dump in entire word. The storage of them produces so many problems (in special environment problems): contaminates lands and water (with heavy metals), so large lands occupy, is blow up by wind (will contamin ...
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Conference12th International Multidisciplinary Scientific Geoconference and EXPO Modern Management of Mine Producing Geology and Environmental Protection Sgem 2012 · December 1, 2012
Into this paper are presented the experimental research regarding the obtaining the building materials with big quantity of fly ash from Timisoara Power Plant, Romania. There are used classical binders (lime and cement) to activate the components of fly as ...
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ConferenceSociety of Petroleum Engineers SPE Russian Oil and Gas Exploration and Production Technical Conference and Exhibition 2012 · January 1, 2012
This paper describes an easy-to-use and fast-track roadmap for Enhanced Oil Recovery (EOR) Prefeasibility Study including (1) screening of EOR suitable methods 2) estimating of additional recovery with mechanistic 3D models 3) evaluating preliminary econom ...
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ConferenceProceedings of the Annual International Symposium on Microarchitecture Micro · December 1, 2010
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, the proposed family of cache coherence protocols can be formally verified cor ...
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ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS · March 13, 2010
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framework for ...
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ConferenceProceedings International Symposium on High Performance Computer Architecture · January 1, 2010
We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction and data ...
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ConferenceACM SIGPLAN Notices · January 1, 2010
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framework for ...
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ConferenceProceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems · December 1, 2007
We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor's functional units. The key insight is that error detection is off the critical path, because an instruction's results are speculative for at least a cyc ...
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ConferenceUsenix 2005 Annual Technical Conference · January 1, 2005
Deadlock can occur wherever multiple processes interact. Most existing static and dynamic deadlock detection tools focus on simple types of deadlock, such as those caused by incorrect ordering of lock acquisitions. In this paper, we propose Pulse, a novel ...
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Conference2004 IEEE International Symposium on Performance Analysis of Systems and Software · June 14, 2004
There is increasing concern among developers that future web servers running commercial workloads may be limited by network processing overhead in the CPU as 10Gb ethernet becomes prevalent. We analyze CPU usage of real hardware running popular commercial ...
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ConferenceAnnual ACM Symposium on Parallel Algorithms and Architectures · December 1, 2003
A model was created for determining criticality in MP systems. An algorithm was devised for computing criticality and criticality of real MP workloads was evaluated. A directed acyclic graph (DAG) model for executing: critical path and slack; mapping DAGs ...
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ConferenceAnnual ACM Symposium on Parallel Algorithms and Architectures · January 1, 2003
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed acyclic graph (DAG) model for characterizing program microexecutions on unip ...
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ConferenceProceedings International Symposium on High Performance Computer Architecture · January 1, 2002
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors. We propose Bandwidth Adaptive Snooping Hybrid (BASH), a hybrid protocol tha ...
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