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FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption

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Ma, J; Xu, C; Liang, N; Wills, LW
Published in: Proceedings International Symposium on Computer Architecture
January 1, 2026

Fully Homomorphic Encryption (FHE) enables secure processing of encrypted data in untrusted cloud environments, but its computational overhead remains a critical bottleneck. The FHE over Torus (TFHE) scheme, originally designed for Boolean gates that each require a costly bootstrapping operation, has been extended to encrypt multi-bit integers, yielding large end-to-end speedups by amortizing bootstrapping cost across many fast linear operations. However, current implementations are constrained to narrow numeric representations because securely supporting wider representations (i.e., beyond 4 bits) demands significantly larger cryptographic parameter sets. We reveal that these new parameters expose fundamental scalability barriers in state-of-the-art spatial accelerators by reshaping internal data dimensions and reuse patterns: scaling computation throughput causes severe memory bandwidth bottlenecks, mismatched data reuse patterns reduce hardware utilization, and buffering massive intermediate states becomes area-prohibitive. To address this, we introduce FlashTFHE, an accelerator featuring a temporal data reuse strategy. By time-multiplexing on-chip key data across parallel bootstrappings, FlashTFHE decouples computational throughput from memory bandwidth constraints. This architecture enables the use of highly efficient functional units and leverages adaptive batching to maximize utilization. FlashTFHE efficiently supports up to 10-bit ciphertexts, achieving speedups of up to 2529× over CPUs, 1320× over GPUs, and 7 × over the state-of-the-art TFHE accelerator.

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Published In

Proceedings International Symposium on Computer Architecture

DOI

EISSN

2575-713X

ISSN

1063-6897

Publication Date

January 1, 2026

Start / End Page

1909 / 1923
 

Citation

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Ma, J., Xu, C., Liang, N., & Wills, L. W. (2026). FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption. In Proceedings International Symposium on Computer Architecture (pp. 1909–1923). https://doi.org/10.1109/ISCA66397.2026.00137
Ma, J., C. Xu, N. Liang, and L. W. Wills. “FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption.” In Proceedings International Symposium on Computer Architecture, 1909–23, 2026. https://doi.org/10.1109/ISCA66397.2026.00137.
Ma J, Xu C, Liang N, Wills LW. FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption. In: Proceedings International Symposium on Computer Architecture. 2026. p. 1909–23.
Ma, J., et al. “FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption.” Proceedings International Symposium on Computer Architecture, 2026, pp. 1909–23. Scopus, doi:10.1109/ISCA66397.2026.00137.
Ma J, Xu C, Liang N, Wills LW. FlashTFHE: A Scalable Architecture for Efficient Multi-Bit Fully Homomorphic Encryption. Proceedings International Symposium on Computer Architecture. 2026. p. 1909–1923.

Published In

Proceedings International Symposium on Computer Architecture

DOI

EISSN

2575-713X

ISSN

1063-6897

Publication Date

January 1, 2026

Start / End Page

1909 / 1923