Hidden Inverses: Coherent Error Cancellation at the Circuit Level
Journal Article (Journal Article)
Coherent gate errors are a concern in many proposed quantum-computing architectures. Here, we show that certain coherent errors can be reduced by a local optimization that chooses between two forms of the same Hermitian and unitary quantum gate. We refer to this method as hidden inverses, and it relies on constructing the same gate from either one sequence of physical operations or the inverted sequence of inverted operations. We use parity-controlled Z rotations as our model circuit and numerically show the utility of hidden inverses as a function of circuit width n. We experimentally demonstrate the effectiveness for n=2 and n=4 qubits in a trapped-ion quantum computer. We numerically compare the method to other gate-level compilations for reducing coherent errors.
Full Text
Duke Authors
Cited Authors
- Zhang, B; Majumder, S; Leung, PH; Crain, S; Wang, Y; Fang, C; Debroy, DM; Kim, J; Brown, KR
Published Date
- March 1, 2022
Published In
Volume / Issue
- 17 / 3
Electronic International Standard Serial Number (EISSN)
- 2331-7019
Digital Object Identifier (DOI)
- 10.1103/PhysRevApplied.17.034074
Citation Source
- Scopus