Unified microprocessor core storage
The organization and management of microprocessor storage structures (e.g., L1 caches, TLBs, etc.) is critical to the performance and energy consumption of the microprocessor. We propose and develop the first microprocessor that can dynamically allocate storage to the structures that need it. First, we replace each existing structure with a dedicated micro-cache (cache) that is smaller than is typical for that structure. With the smaller sizes, these structures can be made faster and less energy-hungry than the original full-size versions. Second, we back up all of the caches with a single Unified Core Storage (UCS). Storage in the multi-banked UCS is dynamically allocated, which alleviates performance bot-tlenecks. The primary benefits of UCS are a significant reduction of storage structure energy (36% less on average) and a modest improvement in performance (9.5% speedup on average). Copyright 2007 ACM.
