Scholars@Duke

• Background
• 

  Education, Training, & Certifications

  • Ph.D., University of Wisconsin - Madison 2002
  • M.S., University of Wisconsin - Madison 1998
  • B.S., Duke University 1996
• 

  Duke Appointment History

  • Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2015 - 2018
  • Associate Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2009 - 2015
  • Associate Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2010 - 2015
  • Assistant Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2002 - 2010
  • Assistant Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2002 - 2009
• Recognition
• 

  In the News

  • JAN 9, 2020

    A Crystal Ball for the Decade Ahead
• 

  Awards & Honors

  • Program Chair of HiPEAC 2017. HiPEAC. 2017
  • Co-chair of selection committee for IEEE Micro's Top Picks 2016. IEEE Micro. 2016
  • Associate Editor in Chief. Computer Architecture Letters. 2015
  • IEEE Micro Top Pick. IEEE Micro. 2015
  • Best Paper Award. 20th International Symposium on High Performance Computer Architecture. 2014
  • IEEE Micro Top Pick. IEEE Micro. 2011
  • Lois and John L. Imhoff Distinguished Teaching Award. Pratt School of Engineering. 2011
  • ACM Senior Member. Association for Computing Machinery. 2009
  • Eta Kappa Nu. Unknown. July 2008
  • Intel Graduate Fellowship. Unknown. July 2008
  • NSF Early CAREER Award. National Science Foundation. July 2008
  • Outstanding Graduate Research Award. University of Wisconsin. July 2008
  • Phi Beta Kappa. Unknown. July 2008
  • Tau Beta Pi. Unknown. July 2008
  • Top of 2004 - Nanocomputing Research. Technology Research News. July 2008
  • Faculty Early Career Development (CAREER) Program. National Science Foundation. 2005
• Research
• 

  Selected Grants

  • SHF: Small: Transforming Computer Architecture Evaluation with Statistical Model Checking awarded by  National Science Foundation 2021 - 2024
  • SHF:Small:Automatic Generation of Cache Coherent Memory Systems for Multicore Processors awarded by  National Science Foundation 2020 - 2023
  • CIF:Small:High Performance Memories that Integrate Coding and Computer Architecture awarded by  National Science Foundation 2017 - 2020
  • SHF:Small:Designing Architectures to be Formally Verifiable awarded by  National Science Foundation 2014 - 2018
  • SHF:Small:Using Coding Theory to Optimize the Representation of Information in Computer Architecture awarded by  National Science Foundation 2014 - 2018
  • SHF:Small:Shared Memory Architectures and Microarchitectures for Heterogeneous General-Purpose Chips awarded by  National Science Foundation 2012 - 2016
  • SHF:Small:Commodity Processors with Mainframe Reliability awarded by  National Science Foundation 2011 - 2015
  • CCF: EAGER: FIESTA: A Sound Multi-Program Workload Methodology awarded by  National Science Foundation 2012 - 2013
  • CPA-CSA: Verification-Aware Microarchitecture awarded by  National Science Foundation 2008 - 2012
  • CAREER: Improving Multiprocessor Availability with Dynamic Verification and Autonomic Operation awarded by  National Science Foundation 2005 - 2011
  • Autonomic Computing via Dynamic Self-Repair of Hardware Faults awarded by National Aeronautics and Space Administration 2005 - 2008
  • ITR: Nanoarchitecture: Balancing Regularity, Complexity, and Defect Tolerance using DNA for Nanoeletronic Integration awarded by  National Science Foundation 2003 - 2007
  • Architectural Support for Service Level Agreements awarded by  National Science Foundation 2003 - 2007
  • FaultFinder: Improving the Availabiltiy of Multiprocessor Servers awarded by  National Science Foundation 2003 - 2006
• 

  External Relationships

  • Morgan & Claypool Publishers
  • Realtime Robotics
  • Wilmer Cutler Pickering Hale
• Publications & Artistic Works
• 

  Selected Publications

  • Academic Articles

    • Sorin, D. J. “Reconfigurable Hardware in Postsilicon Microarchitecture.” Computer 54, no. 3 (March 1, 2021): 4–5. https://doi.org/10.1109/MC.2020.3047006.
       Full Text
    • Mehrabi, A., A. Manocha, B. C. Lee, and D. J. Sorin. “Bayesian Optimization for Efficient Accelerator Synthesis.” Acm Transactions on Architecture and Code Optimization 18, no. 1 (January 1, 2021). https://doi.org/10.1145/3427377.
       Full Text
    • Sorin, D. J. “Computer Architecture for Orbital Edge Computing.” Computer 53, no. 4 (April 1, 2020): 7–8. https://doi.org/10.1109/MC.2020.2969673.
       Full Text
    • Mappouras, G., A. Vahid, R. Calderbank, and D. J. Sorin. “Extending flash lifetime in embedded processors by expanding analog choice.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 11 (November 1, 2018): 2462–73. https://doi.org/10.1109/TCAD.2018.2857059.
       Full Text
    • Sorin, D. J. “Low-Power Content Addressable Memory.” Computer 51, no. 3 (March 1, 2018): 8–9. https://doi.org/10.1109/MC.2018.1731073.
       Full Text
    • Sorin, D. J. “Persistent Memory.” Computer 50, no. 3 (March 1, 2017): 12. https://doi.org/10.1109/MC.2017.67.
       Full Text
    • Martin, M., and D. Sorin. “Top Picks from the 2015 Computer Architecture Conferences.” Ieee Micro 36, no. 3 (May 1, 2016): 6–9. https://doi.org/10.1109/MM.2016.47.
       Full Text
    • Zhang, M., J. D. Bingham, J. Erickson, and D. J. Sorin. “PVCoherence: Designing Flat Coherence Protocols for Scalable Verification.” Ieee Micro 35, no. 3 (May 1, 2015): 84–91. https://doi.org/10.1109/MM.2015.48.
       Full Text
    • Nathan, R., and D. J. Sorin. “Argus-G: Comprehensive, low-cost error detection for GPGPU cores.” Ieee Computer Architecture Letters 14, no. 1 (January 1, 2015): 13–16. https://doi.org/10.1109/LCA.2014.2298391.
       Full Text
    • Nathan, R., and D. J. Sorin. “Nostradamus: Low-cost hardware-only error detection for processor cores.” Proceedings  Design, Automation and Test in Europe, Date, 2014.
    • Sorin, D. J., O. Matthews, and M. Zhang. “Architecting dynamic power management to be formally verifiable.” Proceedings  Design Automation Conference, January 1, 2014. https://doi.org/10.1145/2593069.2596669.
       Full Text
    • Hechtman, B. A., and D. J. Sorin. “Evaluating cache coherent shared virtual memory for heterogeneous multicore chips.” Ispass 2013  Ieee International Symposium on Performance Analysis of Systems and Software, August 19, 2013, 118–19. https://doi.org/10.1109/ISPASS.2013.6557152.
       Full Text
    • Hechtman, B. A., and D. J. Sorin. “Exploring memory consistency for massively-threaded throughput-oriented processors.” Proceedings  International Symposium on Computer Architecture, August 12, 2013, 201–12. https://doi.org/10.1145/2485922.2485940.
       Full Text
    • Jacobvitz, A. N., R. Calderbank, and D. J. Sorin. “Coset coding to extend the lifetime of memory.” Proceedings  International Symposium on High Performance Computer Architecture, July 23, 2013, 222–33. https://doi.org/10.1109/HPCA.2013.6522321.
       Full Text
    • Seetharam, K., L. C. T. Keh, R. Nathan, and D. J. Sorin. “Applying reduced precision arithmetic to detect errors in floating point multiplication.” Proceedings of Ieee Pacific Rim International Symposium on Dependable Computing, Prdc, January 1, 2013, 232–35. https://doi.org/10.1109/PRDC.2013.44.
       Full Text
    • Jacobvitz, A. N., R. Calderbank, and D. J. Sorin. “Writing cosets of a convolutional code to increase the Lifetime of Flash memory.” 2012 50th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2012, December 1, 2012, 308–18. https://doi.org/10.1109/Allerton.2012.6483234.
       Full Text
    • Martin, M. M. K., M. D. Hill, and D. J. Sorin. “Why on-chip cache coherence is here to stay.” Communications of the Acm 55, no. 7 (July 1, 2012): 78–89. https://doi.org/10.1145/2209249.2209269.
       Full Text
    • Eibl, P. J., A. Meixner, and D. J. Sorin. “An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2.” Performance Evaluation Review 39, no. 1 SPEC. ISSUE (July 15, 2011): 121–22. https://doi.org/10.1145/2007116.2007131.
       Full Text
    • Gizopoulos, D., M. Psarakis, S. V. Adve, P. Ramachandran, S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. “Architectures for online error detection and recovery in multicore processors.” Proceedings  Design, Automation and Test in Europe, Date, May 31, 2011, 533–38.
    • Romanescu, B., A. Lebeck, and D. J. Sorin. “Address translation aware memory consistency.” Ieee Micro 31, no. 1 (January 1, 2011): 109–18. https://doi.org/10.1109/MM.2010.99.
       Full Text
    • Sorin, D. J., M. D. Hill, and D. A. Wood. “A primer on memory consistency and cache coherence.” Synthesis Lectures on Computer Architecture 16 (January 1, 2011): 1–212. https://doi.org/10.2200/S00346ED1V01Y201104CAC016.
       Full Text
    • Zhang, M., A. Lebeck, and D. Sorin. “Fractal consistency: Architecting the memory system to facilitate verification.” Ieee Computer Architecture Letters 9, no. 2 (July 1, 2010): 61–64. https://doi.org/10.1109/L-CA.2010.18.
       Full Text  Open Access Copy
    • Eibl, P. J., A. D. Cook, and D. J. Sorin. “Reduced precision checking for a floating point adder.” Proceedings  Ieee International Symposium on Defect and Fault Tolerance in Vlsi Systems, December 1, 2009, 145–52. https://doi.org/10.1109/DFT.2009.22.
       Full Text
    • Zhang, M., A. Lungu, and D. J. Sorin. “Analyzing formal verification and testing efforts of different fault tolerance mechanisms.” Proceedings  Ieee International Symposium on Defect and Fault Tolerance in Vlsi Systems, December 1, 2009, 277–85. https://doi.org/10.1109/DFT.2009.23.
       Full Text
    • Lungu, A., P. Bose, A. Buyuktosunoglu, and D. J. Sorin. “Dynamic power gating with quality guarantees.” Proceedings of the International Symposium on Low Power Electronics and Design, November 24, 2009, 377–82. https://doi.org/10.1145/1594233.1594331.
       Full Text
    • Lungu, A., P. Bose, D. J. Sorin, S. German, and G. Janssen. “Multicore power management: Ensuring robustness via early-stage formal verification.” 2009 7th Ieee Acm International Conference on Formal Methods and Models for Co Design, Memocode ’09, November 19, 2009, 78–87. https://doi.org/10.1109/MEMCOD.2009.5185383.
       Full Text
    • Meixner, A., and D. J. Sorin. “Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures.” Ieee Transactions on Dependable and Secure Computing 6, no. 1 (January 1, 2009): 18–31. https://doi.org/10.1109/TDSC.2007.70243.
       Full Text
    • Romanescu, B. F., M. E. Bauer, S. Ozev, and D. J. Sorin. “Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.” Conference on Computing Frontiers  Proceedings of the 2008 Conference on Computing Frontiers, Cf’08, December 1, 2008, 129–38. https://doi.org/10.1145/1366230.1366257.
       Full Text
    • Romanescu, B. F., and D. J. Sorin. “Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults.” Parallel Architectures and Compilation Techniques  Conference Proceedings, Pact, December 1, 2008, 43–51. https://doi.org/10.1145/1454115.1454124.
       Full Text
    • Meixner, A., and D. J. Sorin. “Detouring: Translating software to circumvent hard faults in simple cores.” Proceedings of the International Conference on Dependable Systems and Networks, October 13, 2008, 80–89. https://doi.org/10.1109/DSN.2008.4630073.
       Full Text
    • Bower, F. A., D. J. Sorin, and L. P. Cox. “The impact of dynamically heterogeneous multicore processors on thread scheduling.” Ieee Micro 28, no. 3 (May 1, 2008): 17–25. https://doi.org/10.1109/MM.2008.46.
       Full Text
    • Meixner, A., M. E. Bauer, and D. J. Sorin. “Argus: Low-cost, comprehensive error detection in simple cores.” Ieee Micro 28, no. 1 (January 1, 2008): 52–59. https://doi.org/10.1109/MM.2008.3.
       Full Text
    • Lungu, A., and D. J. Sorin. “Verification-aware microprocessor design.” Parallel Architectures and Compilation Techniques  Conference Proceedings, Pact, December 1, 2007, 83–93. https://doi.org/10.1109/PACT.2007.17.
       Full Text
    • Meixner, A., M. E. Bauer, and D. J. Sorin. “Argus: Low-cost, comprehensive error detection in simple cores.” Proceedings of the Annual International Symposium on Microarchitecture, Micro, December 1, 2007, 210–22. https://doi.org/10.1109/MICRO.2007.18.
       Full Text
    • Meixner, A., and D. J. Sorin. “Error detection using dynamic dataflow verification.” Parallel Architectures and Compilation Techniques  Conference Proceedings, Pact, December 1, 2007, 104–15. https://doi.org/10.1109/PACT.2007.26.
       Full Text
    • Ozev, S., D. J. Sorin, and M. Yilmaz. “Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.” 2007 Ieee International Conference on Computer Design, Iccd 2007, December 1, 2007, 317–24. https://doi.org/10.1109/ICCD.2007.4601919.
       Full Text
    • Romanescu, B. F., M. E. Bauer, D. J. Sorin, and S. Ozev. “Reducing the impact of process variability with prefetching and criticality-based resource allocation.” Parallel Architectures and Compilation Techniques  Conference Proceedings, Pact, December 1, 2007, 424. https://doi.org/10.1109/PACT.2007.16.
       Full Text
    • Meixner, A., and D. J. Sorin. “Unified microprocessor core storage.” 2007 Computing Frontiers, Conference Proceedings, October 22, 2007, 23–34. https://doi.org/10.1145/1242531.1242538.
       Full Text
    • Meixner, A., and D. J. Sorin. “Error detection via online checking of cache coherence with token coherence signatures.” Proceedings  International Symposium on High Performance Computer Architecture, August 10, 2007, 145–56. https://doi.org/10.1109/HPCA.2007.346193.
       Full Text
    • Bower, F. A., D. J. Sorin, and S. Ozev. “Online Diagnosis of Hard Faults in Microprocessors.” Acm Transactions on Architecture and Code Optimization 4, no. 2 (January 1, 2007): 8. https://doi.org/10.1145/1250727.1250728.
       Full Text
    • Meixner, A., and D. J. Sorin. “Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures.” Proceedings of the International Conference on Dependable Systems and Networks 2006 (December 22, 2006): 73–82. https://doi.org/10.1109/DSN.2006.29.
       Full Text
    • Sadler, N. N., and D. J. Sorin. “Choosing an error protection scheme for a microprocessor's L1 data cache.” Ieee International Conference on Computer Design, Iccd 2006, December 1, 2006, 499–505. https://doi.org/10.1109/ICCD.2006.4380862.
       Full Text
    • Bower, F. A., D. Hower, M. Yilmaz, D. J. Sorin, and S. Ozev. “Applying architectural vulnerability analysis to hard faults in the microprocessor.” Performance Evaluation Review 34, no. 1 (June 1, 2006): 375–76. https://doi.org/10.1145/1140103.1140327.
       Full Text
    • Li, T., A. R. Lebeck, and D. J. Sorin. “Spin detection hardware for improved management of multithreaded systems.” Ieee Transactions on Parallel and Distributed Systems 17, no. 6 (June 1, 2006): 508–21. https://doi.org/10.1109/TPDS.2006.78.
       Full Text
    • Patwardhan, J. P., C. Dwyer, A. R. Lebeck, and D. J. Sorin. “NANA: A nano-scale active network architecture.” Acm Journal on Emerging Technologies in Computing Systems 2, no. 1 (January 1, 2006): 1–30. https://doi.org/10.1145/1126257.1126258.
       Full Text
    • Yilmaz, M., D. R. Hower, S. Ozev, and D. J. Sorin. “Self-checking and self-diagnosing 32-bit microprocessor multiplier.” Proceedings  International Test Conference, January 1, 2006. https://doi.org/10.1109/TEST.2006.297634.
       Full Text
    • Bower, F. A., D. J. Sorin, and S. Ozev. “A mechanism for online diagnosis of hard faults in microprocessors.” Proceedings of the Annual International Symposium on Microarchitecture, Micro, December 1, 2005, 197–208. https://doi.org/10.1109/MICRO.2005.8.
       Full Text
    • Carter, J. R., S. Ozev, and D. J. Sorin. “Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown.” Proceedings  Design, Automation and Test in Europe, Date ’05 I (December 1, 2005): 300–305. https://doi.org/10.1109/DATE.2005.94.
       Full Text
    • Meixner, A., and D. J. Sorin. “Dynamic verification of sequential consistency.” Proceedings  International Symposium on Computer Architecture, November 10, 2005, 482–93. https://doi.org/10.1109/ISCA.2005.25.
       Full Text
    • Bower, F. A., S. Ozev, and D. J. Sorin. “Autonomic microprocessor execution via self-repairing arrays.” Ieee Transactions on Dependable and Secure Computing 2, no. 4 (January 1, 2005): 297–310. https://doi.org/10.1109/TDSC.2005.44.
       Full Text
    • Dwyer, C., A. R. Lebeck, and D. J. Sorin. “Self-assembled architectures and the temporal aspects of computing.” Computer 38, no. 1 (January 1, 2005): 56–64. https://doi.org/10.1109/MC.2005.34.
       Full Text
    • Dwyer, C., M. Cheung, and D. J. Sorin. “Semi-empirical SPICE models for carbon nanotube FET logic.” 2004 4th Ieee Conference on Nanotechnology, December 1, 2004, 386–88.
    • Sorin, D. J., M. M. K. Martin, M. D. Hill, and D. A. Wood. “Using speculation to simplify multiprocessor design.” Proceedings  International Parallel and Distributed Processing Symposium, Ipdps 2004 (Abstracts and Cd Rom) 18 (December 1, 2004): 1057–66.
    • Dwyer, C., V. Johri, M. Cheung, J. Patwardhan, A. Lebeck, and D. Sorin. “Design tools for a DNA-guided self-assembling carbon nanotube technology.” Nanotechnology 15, no. 9 (September 1, 2004): 1240–45. https://doi.org/10.1088/0957-4484/15/9/022.
       Full Text
    • Bower, F. A., P. G. Shealy, S. Ozev, and D. J. Sorin. “Tolerating hard faults in microprocessor array structures.” Proceedings of the International Conference on Dependable Systems and Networks, January 1, 2004, 51–60. https://doi.org/10.1109/dsn.2004.1311876.
       Full Text
    • Sorin, D. J., M. D. Hill, and D. A. Wood. “Dynamic Verification of End-to-End Multiprocessor Invariants.” Proceedings of the International Conference on Dependable Systems and Networks, December 1, 2003, 281–90. https://doi.org/10.1109/DSN.2003.1209938.
       Full Text
    • Alameldeen, A. R., M. M. K. Martin, C. J. Mauer, K. E. Moore, M. Xu, M. D. Hill, D. A. Wood, and D. J. Sorin. “Simulating a $2M commercial server on a $2K PC.” Computer 36, no. 2 (February 1, 2003): 50-57+4. https://doi.org/10.1109/MC.2003.1178046.
       Full Text
    • Sorin, D. J., J. L. Lemon, D. L. Eager, and M. K. Vernon. “Analytic evaluation of shared-memory architectures.” Ieee Transactions on Parallel and Distributed Systems 14, no. 2 (February 1, 2003): 166–80. https://doi.org/10.1109/TPDS.2003.1178880.
       Full Text
    • Martin, M. M. K., P. J. Harper, D. J. Sorin, M. D. Hill, and D. A. Wood. “Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors.” Conference Proceedings  Annual International Symposium on Computer Architecture, Isca, January 1, 2003, 206–17. https://doi.org/10.1145/859639.859642.
       Full Text
    • Sorin, D. J., M. Plakal, A. E. Condon, M. D. Hill, M. M. K. Martin, and D. A. Wood. “Specifying and verifying a broadcast and a multicast snooping cache coherence protocol.” Ieee Transactions on Parallel and Distributed Systems 13, no. 6 (June 1, 2002): 556–78. https://doi.org/10.1109/TPDS.2002.1011412.
       Full Text
    • Sorin, D. J., M. M. K. Martin, M. D. Hill, and D. A. Wood. “SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery.” Conference Proceedings  Annual International Symposium on Computer Architecture, Isca, January 1, 2002, 123–34.
    • Martin, M. M. K., D. J. Sorin, H. W. Cain, M. D. Hill, and M. H. Lipasti. “Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.” Proceedings of the Annual International Symposium on Microarchitecture, December 1, 2001, 328–37. https://doi.org/10.1109/MICRO.2001.991130.
       Full Text
    • Martin, M. M. K., D. J. Sorin, A. Ailamaki, A. R. Alameldeen, R. M. Dickson, C. J. Mauer, K. E. Moore, M. Plakal, M. D. Hill, and D. A. Wood. “Timestamp snooping: An approach for extending SMPs.” International Conference on Architectural Support for Programming Languages and Operating Systems  Asplos, December 1, 2000, 25–36.
    • Eager, D. L., D. J. Sorin, and M. K. Vernon. “AMVA techniques for high service time variability.” Performance Evaluation Review 28, no. 1 (January 1, 2000): 217–28. https://doi.org/10.1145/345063.339418.
       Full Text
    • Martin, M. M. K., D. J. Sorin, A. Ailamaki, A. R. Alameldeen, R. M. Dickson, C. J. Mauer, K. E. Moore, M. Plakal, M. D. Hill, and D. A. Wood. “Timestamp snooping: An approach for extending SMPs.” Sigplan Notices (Acm Special Interest Group on Programming Languages) 35, no. 11 (January 1, 2000): 25–36. https://doi.org/10.1145/356989.356992.
       Full Text
    • Martin, M. M. K., D. J. Sorin, A. Ailamaki, A. R. Alameldeen, R. M. Dickson, C. J. Mauer, K. E. Moore, M. Plakal, M. D. Hill, and D. A. Wood. “Timestamp snooping: An approach for extending SMPs.” Operating Systems Review (Acm) 34, no. 5 (January 1, 2000): 25–36. https://doi.org/10.1145/384264.378998.
       Full Text
    • Bilir, E. E., R. M. Dickson, Y. Hu, M. Plakal, D. J. Sorin, M. D. Hill, and D. A. Wood. “Multicast snooping: A new coherence method using a multicast address network.” Conference Proceedings  Annual International Symposium on Computer Architecture, Isca, January 1, 1999, 294–304.
    • Condon, A. E., M. D. Hill, M. Plakal, and D. J. Sorin. “Using Lamport clocks to reason about relaxed memory models.” Ieee High Performance Computer Architecture Symposium Proceedings, January 1, 1999, 270–78. https://doi.org/10.1109/hpca.1999.744379.
       Full Text
    • Hill, M. D., A. E. Condon, M. Plakal, and D. J. Sorin. “System-level specification framework for I/O architectures.” Annual Acm Symposium on Parallel Algorithms and Architectures, January 1, 1999, 138–47.
    • Plakal, M., D. J. Sorin, A. E. Condon, and M. D. Hill. “Lamport clocks: verifying a directory cache-coherence protocol.” Annual Acm Symposium on Parallel Algorithms and Architectures, January 1, 1998, 67–76.
    • Sorin, D. J., V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood. “Analytic evaluation of shared-memory systems with ILP processors.” Conference Proceedings  Annual International Symposium on Computer Architecture, Isca, January 1, 1998, 380–91.

  • Conference Papers

    • Mehrabi, A., D. Lee, N. Chatterjee, D. J. Sorin, B. C. Lee, and M. O’Connor. “Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures.” In Proceedings  2021 Ieee International Symposium on Performance Analysis of Systems and Software, Ispass 2021, 48–58, 2021. https://doi.org/10.1109/ISPASS51385.2021.00016.
       Full Text
    • Murray, S., G. D. Konidaris, and D. J. Sorin. “Roadmap subsampling for changing environments.” In Ieee International Conference on Intelligent Robots and Systems, 5664–70, 2020. https://doi.org/10.1109/IROS45743.2020.9341431.
       Full Text
    • Archer, S., G. Mappouras, R. Calderbank, and D. Sorin. “Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory.” In Proceedings  50th Annual Ieee/Ifip International Conference on Dependable Systems and Networks, Dsn 2020, 331–42, 2020. https://doi.org/10.1109/DSN48063.2020.00049.
       Full Text
    • Oswald, N., V. Nagarajan, and D. J. Sorin. “HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols.” In Proceedings  International Symposium on Computer Architecture, 2020-May:888–99, 2020. https://doi.org/10.1109/ISCA45697.2020.00077.
       Full Text
    • Mehrabi, A., A. Manocha, B. C. Lee, and D. J. Sorin. “Prospector: Synthesizing Efficient Accelerators via Statistical Learning.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 151–56, 2020. https://doi.org/10.23919/DATE48585.2020.9116473.
       Full Text
    • Murray, S., W. Floyd-Jones, G. Konidaris, and D. J. Sorin. “A programmable architecture for robot motion planning acceleration.” In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors, 2019-July:185–88, 2019. https://doi.org/10.1109/ASAP.2019.000-4.
       Full Text
    • Mappouras, G., A. Vahid, R. Calderbank, and D. J. Sorin. “GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors.” In Proceedings  49th Annual Ieee/Ifip International Conference on Dependable Systems and Networks, Dsn 2019, 1–12, 2019. https://doi.org/10.1109/DSN.2019.00016.
       Full Text
    • Oswald, N., V. Nagarajan, and D. J. Sorin. “ProtoGen: Automatically generating directory cache coherence protocols from atomic specifications.” In Proceedings  International Symposium on Computer Architecture, 247–60, 2018. https://doi.org/10.1109/ISCA.2018.00030.
       Full Text
    • Mappouras, G., A. Vahid, R. Calderbank, D. R. Hower, and D. J. Sorin. “Jenga: Efficient fault tolerance for stacked DRAM.” In Proceedings  35th Ieee International Conference on Computer Design, Iccd 2017, 361–68, 2017. https://doi.org/10.1109/ICCD.2017.62.
       Full Text
    • Matthews, O., and D. J. Sorin. “Architecting hierarchical coherence protocols for push-button parametric verification.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, Part F131207:477–89, 2017. https://doi.org/10.1145/3123939.3123971.
       Full Text
    • Matthews, O., J. Bingham, and D. J. Sorin. “Verifiable hierarchical protocols with network invariants on parametric systems.” In Proceedings of the 16th Conference on Formal Methods in Computer Aided Design, Fmcad 2016, 101–8, 2017. https://doi.org/10.1109/FMCAD.2016.7886667.
       Full Text
    • Murray, S., W. Floyd-Jones, Y. Qi, G. Konidaris, and D. J. Sorin. “The microarchitecture of a real-Time robot motion planning accelerator.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, Vol. 2016-December, 2016. https://doi.org/10.1109/MICRO.2016.7783748.
       Full Text
    • Mappouras, G., A. Vahid, R. Calderbank, and D. J. Sorin. “Methuselah flash: Rewriting codes for extra long storage lifetime.” In Proceedings  46th Annual Ieee/Ifip International Conference on Dependable Systems and Networks, Dsn 2016, 180–91, 2016. https://doi.org/10.1109/DSN.2016.25.
       Full Text
    • Murray, S., W. Floyd-Jones, Y. Qi, D. Sorin, G. Konidaris, and D. Robotics. “Robot motion planning on a chip.” In Robotics: Science and Systems, Vol. 12, 2016.
    • Eslami, A., A. Velasco, A. Vahid, G. Mappouras, R. Calderbank, and D. J. Sorin. “Writing without disturb on phase change memories by integrating coding and layout design.” In Acm International Conference Proceeding Series, 05-08-October-2015:71–77, 2015. https://doi.org/10.1145/2818950.2818962.
       Full Text
    • Jacobvitz, A. N., A. D. Hilton, and D. J. Sorin. “Multi-program benchmark definition.” In Ispass 2015  Ieee International Symposium on Performance Analysis of Systems and Software, 72–82, 2015. https://doi.org/10.1109/ISPASS.2015.7095786.
       Full Text  Open Access Copy
    • Nathan, R., B. Anthonio, S. L. Lu, H. Naeimi, D. J. Sorin, and X. Sun. “Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.” In International Conference for High Performance Computing, Networking, Storage and Analysis, Sc, 2015-January:117–27, 2014. https://doi.org/10.1109/SC.2014.15.
       Full Text
    • Matthews, O., M. Zhang, and D. J. Sorin. “Scalably verifiable dynamic power management.” In Proceedings  International Symposium on High Performance Computer Architecture, 579–90, 2014. https://doi.org/10.1109/HPCA.2014.6835967.
       Full Text
    • Nathan, R., and D. J. Sorin. “Nostradamus: Low-cost hardware-only error detection for processor cores.” In Proceedings  Design, Automation and Test in Europe, Date, 2014. https://doi.org/10.7873/DATE2014.173.
       Full Text
    • Zhang, M., J. D. Bingham, J. Erickson, and D. J. Sorin. “PVCoherence: Designing flat coherence protocols for scalable verification.” In Proceedings  International Symposium on High Performance Computer Architecture, 392–403. IEEE Computer Society, 2014. https://doi.org/10.1109/HPCA.2014.6835949.
       Full Text
    • Badea, C., L. Iures, and D. Sorin. “The recycling of fly ash to obtain building materials.” In International Multidisciplinary Scientific Geoconference Surveying Geology and Mining Ecology Management, Sgem, 473–78, 2013. https://doi.org/10.5593/SGEM2013/BD4/S18.025.
       Full Text
    • Catalin, B., I. Liana, B. Ionel, and D. Sorin. “Building materials realised with fly ash.” In 12th International Multidisciplinary Scientific Geoconference and Expo  Modern Management of Mine Producing, Geology and Environmental Protection, Sgem 2012, 4:661–65, 2012.
    • Lefebvre, C., P. Lemouzy, D. Sorin, G. Roy, and S. Serbutoviez. “Building a roadmap for enhanced oil recovery prefeasibility study.” In Society of Petroleum Engineers  Spe Russian Oil and Gas Exploration and Production Technical Conference and Exhibition 2012, 1:160–90, 2012. https://doi.org/10.2118/159264-ms.
       Full Text
    • Zhang, M., A. R. Lebeck, and D. J. Sorin. “Fractal Coherence: Scalably verifiable cache coherence.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 471–82, 2010. https://doi.org/10.1109/MICRO.2010.11.
       Full Text
    • Romanescu, B. F., A. R. Lebeck, and D. J. Sorin. “Specifying and dynamically verifying address translation-aware memory consistency.” In International Conference on Architectural Support for Programming Languages and Operating Systems  Asplos, 323–34, 2010. https://doi.org/10.1145/1736020.1736057.
       Full Text
    • Romanescu, B. F., A. R. Lebeck, D. J. Sorin, and A. Bracy. “Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.” In Proceedings  International Symposium on High Performance Computer Architecture, 2010. https://doi.org/10.1109/hpca.2010.5416643.
       Full Text  Open Access Copy
    • Romanescu, B. F., A. R. Lebeck, and D. J. Sorin. “Specifying and dynamically verifying address translation-aware memory consistency.” In Acm Sigplan Notices, 45:323–34, 2010. https://doi.org/10.1145/1735971.1736057.
       Full Text
    • Yilmaz, M., A. Meixner, S. Ozev, and D. J. Sorin. “Lazy error detection for microprocessor functional units.” In Proceedings  Ieee International Symposium on Defect and Fault Tolerance in Vlsi Systems, 361–69, 2007. https://doi.org/10.1109/DFT.2007.16.
       Full Text
    • Li, T., C. S. Ellis, A. R. Lebeck, and D. J. Sorin. “Pulse: A dynamic deadlock detection mechanism using speculative execution.” In Usenix 2005 Annual Technical Conference, 31–44, 2005.
    • Patwardhan, J. P., A. R. Lebeck, and D. J. Sorin. “Communication breakdown: Analyzing CPU usage in commercial web workloads.” In 2004 Ieee International Symposium on Performance Analysis of Systems and Software, 12–19, 2004. https://doi.org/10.1109/ISPASS.2004.1291351.
       Full Text
    • Li, T., A. R. Lebeck, and D. J. Sorin. “Quantifying instruction criticality for shared memory multiprocessors.” In Annual Acm Symposium on Parallel Algorithms and Architectures, 47–72, 2003.
    • Li, T., A. R. Lebeck, and D. J. Sorin. “Quantifying instruction criticality for shared memory multiprocessors.” In Annual Acm Symposium on Parallel Algorithms and Architectures, 128–37, 2003. https://doi.org/10.1145/777412.777434.
       Full Text
    • Martin, M. M. K., D. J. Sorin, M. D. Hill, and D. A. Wood. “Bandwidth adaptive snooping.” In Proceedings  International Symposium on High Performance Computer Architecture, 2002-January:251–62, 2002. https://doi.org/10.1109/HPCA.2002.995715.
       Full Text
• Teaching & Mentoring
• 

  Recent Courses

  • COMPSCI 250D: Computer Architecture 2021
  • COMPSCI 391: Independent Study 2021
  • ECE 250D: Computer Architecture 2021
  • ECE 552: Advanced Computer Architecture I 2021
  • ECE 552: Advanced Computer Architecture I 2020
  • ECE 652: Advanced Computer Architecture II 2020
  • COMPSCI 250D: Computer Architecture 2019
  • ECE 250D: Computer Architecture 2019
  • ECE 554: Fault-Tolerant and Testable Computer Systems 2019

Some information on this profile has been compiled automatically from Duke databases and external sources. (Our About page explains how this works.) If you see a problem with the information, please write to Scholars@Duke and let us know. We will reply promptly.