Daniel J. Sorin | Scholars@Duke

Daniel J. Sorin
Addy Professor of Electrical and Computer Engineering in the Edmund T. Pratt, Jr. School of Engineering

Dr. Daniel Sorin is the Addy Professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.

Current Appointments & Affiliations

Addy Professor of Electrical and Computer Engineering in the Edmund T. Pratt, Jr. School of Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017 - 2019
Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2015

Contact Information

209C Hudson Hall, Durham, NC 27708
Box 90291, Durham, NC 27708-0291
sorin@ee.duke.edu (919) 660-5439
http://www.ee.duke.edu/~sorin

Background
Education, Training, & Certifications
- Ph.D., University of Wisconsin at Madison 2002
- M.S., University of Wisconsin at Madison 1998
- B.S., Duke University 1996
Duke Appointment History
- Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2015 - 2018
- Associate Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2009 - 2015
- Associate Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2010 - 2015
- Assistant Professor in the Department of Computer Science, Computer Science, Trinity College of Arts & Sciences 2002 - 2010
- Assistant Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2002 - 2009
Recognition
Awards & Honors
- Program Chair of HiPEAC 2017. HiPEAC. 2017
- Co-chair of selection committee for IEEE Micro's Top Picks 2016. IEEE Micro. 2016
- Associate Editor in Chief. Computer Architecture Letters. 2015
- IEEE Micro Top Pick. IEEE Micro. 2015
- Best Paper Award. 20th International Symposium on High Performance Computer Architecture. 2014
- IEEE Micro Top Pick. IEEE Micro. 2011
- Lois and John L. Imhoff Distinguished Teaching Award. Pratt School of Engineering. 2011
- ACM Senior Member. Association for Computing Machinery. 2009
- Eta Kappa Nu. Unknown. July 2008
- Intel Graduate Fellowship. Unknown. July 2008
- NSF Early CAREER Award. National Science Foundation. July 2008
- Outstanding Graduate Research Award. University of Wisconsin. July 2008
- Phi Beta Kappa. Unknown. July 2008
- Tau Beta Pi. Unknown. July 2008
- Top of 2004 - Nanocomputing Research. Technology Research News. July 2008
- Faculty Early Career Development (CAREER) Program. National Science Foundation. 2005
Research
Selected Grants
- CIF:Small:High Performance Memories that Integrate Coding and Computer Architecture awarded by National Science Foundation 2017 - 2020
- SHF:Small:Designing Architectures to be Formally Verifiable awarded by National Science Foundation 2014 - 2018
- SHF:Small:Using Coding Theory to Optimize the Representation of Information in Computer Architecture awarded by National Science Foundation 2014 - 2018
- SHF:Small:Shared Memory Architectures and Microarchitectures for Heterogeneous General-Purpose Chips awarded by National Science Foundation 2012 - 2016
- SHF:Small:Commodity Processors with Mainframe Reliability awarded by National Science Foundation 2011 - 2015
- CCF: EAGER: FIESTA: A Sound Multi-Program Workload Methodology awarded by National Science Foundation 2012 - 2013
- CPA-CSA: Verification-Aware Microarchitecture awarded by National Science Foundation 2008 - 2012
- CAREER: Improving Multiprocessor Availability with Dynamic Verification and Autonomic Operation awarded by National Science Foundation 2005 - 2011
- Autonomic Computing via Dynamic Self-Repair of Hardware Faults awarded by National Aeronautics and Space Administration 2005 - 2008
- ITR: Nanoarchitecture: Balancing Regularity, Complexity, and Defect Tolerance using DNA for Nanoeletronic Integration awarded by National Science Foundation 2003 - 2007
- Architectural Support for Service Level Agreements awarded by National Science Foundation 2003 - 2007
- FaultFinder: Improving the Availabiltiy of Multiprocessor Servers awarded by National Science Foundation 2003 - 2006
Publications & Artistic Works
Selected Publications
- Academic Articles
  - Mappouras, G, Vahid, A, Calderbank, R, and Sorin, DJ. "Extending flash lifetime in embedded processors by expanding analog choice." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 11 (November 1, 2018): 2462-2473. Full Text
  - Sorin, DJ. "Low-Power Content Addressable Memory." Computer 51, no. 3 (March 1, 2018): 8-9. Full Text
  - Sorin, DJ. "Persistent Memory." Computer 50, no. 3 (March 1, 2017): 12-null. Full Text
  - Martin, M, and Sorin, D. "Top Picks from the 2015 Computer Architecture Conferences." Ieee Micro 36, no. 3 (May 2016): 6-9. Full Text
  - Zhang, M, Bingham, JD, Erickson, J, and Sorin, DJ. "PVCoherence: Designing Flat Coherence Protocols for Scalable Verification." Ieee Micro 35, no. 3 (May 1, 2015): 84-91. Full Text
  - Nathan, R, and Sorin, DJ. "Argus-G: Comprehensive, low-cost error detection for GPGPU cores." Ieee Computer Architecture Letters 14, no. 1 (January 1, 2015): 13-16. Full Text
  - Nathan, R, and Sorin, DJ. "Nostradamus: Low-cost hardware-only error detection for processor cores." Proceedings -Design, Automation and Test in Europe, DATE (2014).
  - Sorin, DJ, Matthews, O, and Zhang, M. "Architecting dynamic power management to be formally verifiable." Proceedings Design Automation Conference (January 1, 2014). Full Text
  - Jacobvitz, AN, Calderbank, R, and Sorin, DJ. "Coset coding to extend the lifetime of memory." Proceedings International Symposium on High Performance Computer Architecture (July 23, 2013): 222-233. Full Text
  - Hechtman, BA, and Sorin, DJ. "Evaluating cache coherent shared virtual memory for heterogeneous multicore chips." 2013 Ieee International Symposium on Performance Analysis of Systems and Software (Ispass) (April 2013). Full Text
  - Hechtman, BA, and Sorin, DJ. "Exploring memory consistency for massively-threaded throughput-oriented processors." Proceedings of the 40th Annual International Symposium on Computer Architecture Isca '13 (2013). Full Text
  - Seetharam, K, Keh, LCT, Nathan, R, and Sorin, DJ. "Applying reduced precision arithmetic to detect errors in floating point multiplication." Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC (January 1, 2013): 232-235. Full Text
  - Jacobvitz, AN, Calderbank, R, and Sorin, DJ. "Writing cosets of a convolutional code to increase the Lifetime of Flash memory." 2012 50th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2012 (December 1, 2012): 308-318. Full Text
  - Martin, MMK, Hill, MD, and Sorin, DJ. "Why on-chip cache coherence is here to stay." Communications of the Acm 55, no. 7 (July 1, 2012): 78-89. Full Text
  - Eibl, PJ, Meixner, A, and Sorin, DJ. "An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2." Performance Evaluation Review 39, no. 1 SPEC. ISSUE (July 15, 2011): 121-122. Full Text
  - Gizopoulos, D, Psarakis, M, Adve, SV, Ramachandran, P, Hari, SKS, Sorin, D, Meixner, A, Biswas, A, and Vera, X. "Architectures for online error detection and recovery in multicore processors." Proceedings Design, Automation and Test in Europe, Date (May 31, 2011): 533-538.
  - Romanescu, B, Lebeck, A, and Sorin, DJ. "Address translation aware memory consistency." Ieee Micro 31, no. 1 (January 1, 2011): 109-118. Full Text
  - Sorin, DJ, Hill, MD, and Wood, DA. "A primer on memory consistency and cache coherence." Synthesis Lectures on Computer Architecture 16 (January 1, 2011): 1-212. Full Text
  - Zhang, M, Lebeck, A, and Sorin, D. "Fractal consistency: Architecting the memory system to facilitate verification." Ieee Computer Architecture Letters 9, no. 2 (July 1, 2010): 61-64. Full Text Open Access Copy
  - Eibl, PJ, Cook, AD, and Sorin, DJ. "Reduced precision checking for a floating point adder." Proceedings Ieee International Symposium on Defect and Fault Tolerance in Vlsi Systems (December 1, 2009): 145-152. Full Text
  - Lungu, A, Bose, P, Buyuktosunoglu, A, and Sorin, DJ. "Dynamic power gating with quality guarantees." Proceedings of the International Symposium on Low Power Electronics and Design (November 24, 2009): 377-382. Full Text
  - Lungu, A, Bose, P, Sorin, DJ, German, S, and Janssen, G. "Multicore power management: Ensuring robustness via early-stage formal verification." 2009 7th Ieee Acm International Conference on Formal Methods and Models for Co Design, Memocode '09 (November 19, 2009): 78-87. Full Text
  - Zhang, M, Lungu, A, and Sorin, DJ. "Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms." 2009 24th Ieee International Symposium on Defect and Fault Tolerance in Vlsi Systems (October 2009). Full Text
  - Meixner, A, and Sorin, DJ. "Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures." Ieee Transactions on Dependable and Secure Computing 6, no. 1 (January 1, 2009): 18-31. Full Text
  - Romanescu, BF, Bauer, ME, Ozev, S, and Sorin, DJ. "Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching." Conference on Computing Frontiers Proceedings of the 2008 Conference on Computing Frontiers, Cf'08 (December 1, 2008): 129-138. Full Text
  - Meixner, A, and Sorin, DJ. "Detouring: Translating software to circumvent hard faults in simple cores." Proceedings of the International Conference on Dependable Systems and Networks (October 13, 2008): 80-89. Full Text
  - Bower, FA, Sorin, DJ, and Cox, LP. "The impact of dynamically heterogeneous multicore processors on thread scheduling." Ieee Micro 28, no. 3 (May 1, 2008): 17-25. Full Text
  - Meixner, A, Bauer, ME, and Sorin, DJ. "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores." Ieee Micro 28, no. 1 (January 2008): 52-59. Full Text
  - Romanescu, BF, and Sorin, DJ. "Core cannibalization architecture." Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques Pact '08 (2008). Full Text
  - "Error detection using dynamic dataflow verification." Parallel Architectures and Compilation Techniques Conference Proceedings, Pact (December 1, 2007): 104-115. Full Text
  - Lungu, A, and Sorin, DJ. "Verification-aware microprocessor design." Parallel Architectures and Compilation Techniques Conference Proceedings, Pact (December 1, 2007): 83-93. Full Text
  - Meixner, A, Bauer, ME, and Sorin, DJ. "Argus: Low-cost, comprehensive error detection in simple cores." Proceedings of the Annual International Symposium on Microarchitecture, Micro (December 1, 2007): 210-222. Full Text
  - Ozev, S, Sorin, DJ, and Yilmaz, M. "Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor." 2007 Ieee International Conference on Computer Design, Iccd 2007 (December 1, 2007): 317-324. Full Text
  - Romanescu, BF, Bauer, ME, Sorin, DJ, and Ozev, S. "Reducing the impact of process variability with prefetching and criticality-based resource allocation." Parallel Architectures and Compilation Techniques Conference Proceedings, Pact (December 1, 2007): 424-null. Full Text
  - Yilmaz, M, Hower, DR, Ozev, S, and Sorin, DJ. "Self-checking and self-diagnosing 32-bit microprocessor multiplier." Proceedings International Test Conference (December 1, 2007). Full Text
  - Meixner, A, and Sorin, DJ. "Error detection via online checking of cache coherence with token coherence signatures." Proceedings International Symposium on High Performance Computer Architecture (August 10, 2007): 145-156. Full Text
  - Bower, FA, Sorin, DJ, and Ozev, S. "Online Diagnosis of Hard Faults in Microprocessors." Acm Transactions on Architecture and Code Optimization 4, no. 2 (January 1, 2007): 8-null. Full Text
  - Meixner, A, and Sorin, DJ. "Unified microprocessor core storage." Proceedings of the 4th International Conference on Computing Frontiers Cf '07 (2007). Full Text
  - Meixner, A, and Sorin, DJ. "Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures." Proceedings of the International Conference on Dependable Systems and Networks 2006 (December 22, 2006): 73-82. Full Text
  - Sadler, NN, and Sorin, DJ. "Choosing an error protection scheme for a microprocessor's L1 data cache." Ieee International Conference on Computer Design, Iccd 2006 (December 1, 2006): 499-505. Full Text
  - Patwardhan, JP, Dwyer, C, Lebeck, AR, and Sorin, DJ. "NANA: A nano-scale active network architecture." Acm Journal on Emerging Technologies in Computing Systems 2, no. 1 (June 28, 2006): 1-30. (Review)
  - Bower, FA, Hower, D, Yilmaz, M, Sorin, DJ, and Ozev, S. "Applying architectural vulnerability analysis to hard faults in the microprocessor." Performance Evaluation Review 34, no. 1 (June 1, 2006): 375-376. Full Text
  - Li, T, Lebeck, AR, and Sorin, DJ. "Spin detection hardware for improved management of multithreaded systems." Ieee Transactions on Parallel and Distributed Systems 17, no. 6 (June 1, 2006): 508-521. Full Text
  - Bower, FA, Sorin, DJ, and Ozev, S. "A mechanism for online diagnosis of hard faults in microprocessors." Proceedings of the Annual International Symposium on Microarchitecture, Micro (December 1, 2005): 197-208. Full Text
  - Carter, JR, Ozev, S, and Sorin, DJ. "Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown." Proceedings Design, Automation and Test in Europe, Date '05 I (December 1, 2005): 300-305. Full Text
  - Meixner, A, and Sorin, DJ. "Dynamic verification of sequential consistency." Proceedings International Symposium on Computer Architecture (November 10, 2005): 482-493. Full Text
  - Bower, FA, Ozev, S, and Sorin, DJ. "Autonomic microprocessor execution via self-repairing arrays." Ieee Transactions on Dependable and Secure Computing 2, no. 4 (October 1, 2005): 297-310. Full Text
  - Dwyer, C, Lebeck, AR, and Sorin, DJ. "Self-assembled architectures and the temporal aspects of computing." Computer 38, no. 1 (January 1, 2005): 56-64. Full Text
  - Dwyer, C, Cheung, M, and Sorin, DJ. "Semi-empirical SPICE models for carbon nanotube FET logic." 2004 4th Ieee Conference on Nanotechnology (December 1, 2004): 386-388.
  - Sorin, DJ, Martin, MMK, Hill, MD, and Wood, DA. "Using speculation to simplify multiprocessor design." Proceedings International Parallel and Distributed Processing Symposium, Ipdps 2004 (Abstracts and Cd Rom) 18 (December 1, 2004): 1057-1066.
  - Bower, FA, Shealy, PG, Ozev, S, and Sorin, DJ. "Tolerating hard faults in microprocessor array structures." Proceedings of the International Conference on Dependable Systems and Networks (October 1, 2004): 51-60.
  - Dwyer, C, Johri, V, Cheung, M, Patwardhan, J, Lebeck, A, and Sorin, D. "Design tools for a DNA-guided self-assembling carbon nanotube technology." Nanotechnology 15, no. 9 (September 1, 2004): 1240-1245. Full Text
  - Sorin, DJ, Hill, MD, and Wood, DA. "Dynamic Verification of End-to-End Multiprocessor Invariants." Proceedings of the International Conference on Dependable Systems and Networks (December 1, 2003): 281-290. Full Text
  - "Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors." Conference Proceedings Annual International Symposium on Computer Architecture, Isca (July 17, 2003): 206-217.
  - Alameldeen, AR, Martin, MMK, Mauer, CJ, Moore, KE, Xu, M, Hill, MD, Wood, DA, and Sorin, DJ. "Simulating a $2M commercial server on a $2K PC." Computer 36, no. 2 (February 1, 2003): 50-57+4. Full Text
  - Sorin, DJ, Lemon, JL, Eager, DL, and Vernon, MK. "Analytic evaluation of shared-memory architectures." Ieee Transactions on Parallel and Distributed Systems 14, no. 2 (February 1, 2003): 166-180. Full Text
  - Sorin, DJ, Plakal, M, Condon, AE, Hill, MD, Martin, MMK, and Wood, DA. "Specifying and verifying a broadcast and a multicast snooping cache coherence protocol." Ieee Transactions on Parallel and Distributed Systems 13, no. 6 (June 1, 2002): 556-578. Full Text
  - Sorin, DJ, Martin, MMK, Hill, MD, and Wood, DA. "SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery." Conference Proceedings Annual International Symposium on Computer Architecture, Isca (January 1, 2002): 123-134.
  - Martin, MMK, Sorin, DJ, Cain, HW, Hill, MD, and Lipasti, MH. "Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing." Proceedings of the Annual International Symposium on Microarchitecture (December 1, 2001): 328-337. Full Text
  - Martin, MMK, Sorin, DJ, Ailamaki, A, Alameldeen, AR, Dickson, RM, Mauer, CJ, Moore, KE, Plakal, M, Hill, MD, and Wood, DA. "Timestamp snooping: An approach for extending SMPs." International Conference on Architectural Support for Programming Languages and Operating Systems Asplos (December 1, 2000): 25-36.
  - Eager, DL, Sorin, DJ, and Vernon, MK. "AMVA techniques for high service time variability." Performance Evaluation Review 28, no. 1 (January 1, 2000): 217-228. Full Text
  - Martin, MMK, Sorin, DJ, Ailamaki, A, Alameldeen, AR, Dickson, RM, Mauer, CJ, Moore, KE, Plakal, M, Hill, MD, and Wood, DA. "Timestamp snooping: An approach for extending SMPs." Sigplan Notices (Acm Special Interest Group on Programming Languages) 35, no. 11 (January 1, 2000): 25-36. Full Text
  - Martin, MMK, Sorin, DJ, Ailamaki, A, Alameldeen, AR, Dickson, RM, Mauer, CJ, Moore, KE, Plakal, M, Hill, MD, and Wood, DA. "Timestamp snooping: An approach for extending SMPs." Operating Systems Review (Acm) 34, no. 5 (January 1, 2000): 25-36. Full Text
  - Bilir, EE, Dickson, RM, Hu, Y, Plakal, M, Sorin, DJ, Hill, MD, and Wood, DA. "Multicast snooping: A new coherence method using a multicast address network." Conference Proceedings Annual International Symposium on Computer Architecture, Isca (January 1, 1999): 294-304.
  - Condon, AE, Hill, MD, Plakal, M, and Sorin, DJ. "Using Lamport clocks to reason about relaxed memory models." Ieee High Performance Computer Architecture Symposium Proceedings (January 1, 1999): 270-278.
  - Hill, MD, Condon, AE, Plakal, M, and Sorin, DJ. "System-level specification framework for I/O architectures." Annual Acm Symposium on Parallel Algorithms and Architectures (January 1, 1999): 138-147.
  - Plakal, M, Sorin, DJ, Condon, AE, and Hill, MD. "Lamport clocks: verifying a directory cache-coherence protocol." Annual Acm Symposium on Parallel Algorithms and Architectures (January 1, 1998): 67-76.
  - Sorin, DJ, Pai, VS, Adve, SV, Vernon, MK, and Wood, DA. "Analytic evaluation of shared-memory systems with ILP processors." Conference Proceedings Annual International Symposium on Computer Architecture, Isca (January 1, 1998): 380-391.
- Conference Papers
  - Oswald, N, Nagarajan, V, and Sorin, DJ. "ProtoGen: Automatically generating directory cache coherence protocols from atomic specifications." July 19, 2018. Full Text
  - Mappouras, G, Vahid, A, Calderbank, R, Hower, DR, and Sorin, DJ. "Jenga: Efficient Fault Tolerance for Stacked DRAM." 2017 IEEE 35th International Conference on Computer Design (ICCD). November 5, 2017 - November 8, 2017.: IEEE, November 2017. Full Text
  - Matthews, O, and Sorin, DJ. "Architecting hierarchical coherence protocols for push-button parametric verification." October 14, 2017. Full Text
  - Matthews, O, Bingham, J, and Sorin, DJ. "Verifiable hierarchical protocols with network invariants on parametric systems." March 24, 2017. Full Text
  - Murray, S, Floyd-Jones, W, Qi, Y, Konidaris, G, and Sorin, DJ. "The microarchitecture of a real-time robot motion planning accelerator." 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). October 15, 2016 - October 19, 2016.: IEEE, October 2016. Full Text
  - Mappouras, G, Vahid, A, Calderbank, R, and Sorin, DJ. "Methuselah flash: Rewriting codes for extra long storage lifetime." September 29, 2016. Full Text
  - Murray, S, Floyd-Jones, W, Qi, Y, Sorin, D, Konidaris, G, and Robotics, D. "Robot motion planning on a chip." January 1, 2016.
  - Eslami, A, Velasco, A, Vahid, A, Mappouras, G, Calderbank, R, and Sorin, DJ. "Writing without disturb on phase change memories by integrating coding and layout design." October 5, 2015. Full Text
  - Jacobvitz, AN, Hilton, AD, and Sorin, DJ. "Multi-program benchmark definition." 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). March 29, 2015 - March 31, 2015.: IEEE, March 2015. Full Text Open Access Copy
  - Matthews, O, Zhang, M, and Sorin, DJ. "Scalably verifiable dynamic power management." 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). February 15, 2014 - February 19, 2014.: IEEE, February 2014. Full Text
  - Nathan, R, Anthonio, B, Lu, SL, Naeimi, H, Sorin, DJ, and Sun, X. "Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy." January 16, 2014. Full Text
  - Nathan, R, and Sorin, DJ. "Nostradamus: Low-cost hardware-only error detection for processor cores." January 1, 2014. Full Text
  - Zhang, M, Bingham, JD, Erickson, J, and Sorin, DJ. "PVCoherence: Designing flat coherence protocols for scalable verification." : IEEE Computer Society, 2014. Full Text
  - Badea, C, Iures, L, and Sorin, D. "The recycling of fly ash to obtain building materials." December 1, 2013. Full Text
  - Catalin, B, Liana, I, Ionel, B, and Sorin, D. "Building materials realised with fly ash." December 1, 2012.
  - Lefebvre, C, Lemouzy, P, Sorin, D, Roy, G, and Serbutoviez, S. "Building a roadmap for enhanced oil recovery prefeasibility study." December 1, 2012.
  - Zhang, M, Lebeck, AR, and Sorin, DJ. "Fractal Coherence: Scalably verifiable cache coherence." December 1, 2010. Full Text
  - Romanescu, BF, Lebeck, AR, and Sorin, DJ. "Specifying and dynamically verifying address translation-aware memory consistency." May 19, 2010. Full Text
  - Romanescu, BF, Lebeck, AR, and Sorin, DJ. "Specifying and dynamically verifying address translation-aware memory consistency." March 1, 2010.
  - Romanescu, BF, Lebeck, AR, Sorin, DJ, and Bracy, A. "Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all." 2010. Open Access Copy
  - Yilmaz, M, Meixner, A, Ozev, S, and Sorin, DJ. "Lazy Error Detection for Microprocessor Functional Units." 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007). September 26, 2007 - September 28, 2007.: IEEE, September 2007. Full Text
  - Patwardhan, JP, Lebeck, AR, and Sorin, DJ. "Communication breakdown: Analyzing CPU usage in commercial web workloads." June 14, 2004. Full Text
  - Li, T, Lebeck, AR, and Sorin, DJ. "Quantifying instruction criticality for shared memory multiprocessors." December 1, 2003.
  - Li, T, Lebeck, AR, and Sorin, DJ. "Quantifying instruction criticality for shared memory multiprocessors." July 28, 2003.
  - Martin, MMK, Sorin, DJ, Hill, MD, and Wood, DA. "Bandwidth adaptive snooping." January 1, 2002. Full Text
Teaching & Mentoring
Recent Courses

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Education, Training, & Certifications

Duke Appointment History

Awards & Honors

Selected Grants

Selected Publications

Academic Articles

Conference Papers

Recent Courses