Lazy error detection for microprocessor functional units

Conference Paper

We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor's functional units. The key insight is that error detection is off the critical path, because an instruction's results are speculative for at least a cycle after being computed. The time between computing and committing the results can be used to lazily detect errors, and laziness allows us to use cheaper error detection logic. We show that lazy error detection is feasible, we develop a low-cost mechanism for detecting errors in adders that exploits laziness, and we show that an existing error detection scheme for multipliers can exploit laziness. © 2007 IEEE.

Full Text

Duke Authors

Cited Authors

  • Yilmaz, M; Meixner, A; Ozev, S; Sorin, DJ

Published Date

  • December 1, 2007

Published In

Start / End Page

  • 361 - 369

International Standard Serial Number (ISSN)

  • 1550-5774

International Standard Book Number 10 (ISBN-10)

  • 0769528856

International Standard Book Number 13 (ISBN-13)

  • 9780769528854

Digital Object Identifier (DOI)

  • 10.1109/DFT.2007.16

Citation Source

  • Scopus