IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS
Publication
, Journal Article
Fair, RB; Wortman, JJ; Liu, J; Tischler, M; Masnari, NA; Duh, KY
Published in: IEEE Transactions on Electron Devices
January 1, 1983
Duke Scholars
Published In
IEEE Transactions on Electron Devices
DOI
EISSN
1557-9646
ISSN
0018-9383
Publication Date
January 1, 1983
Volume
30
Issue
11
Start / End Page
1584 / 1585
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering
Citation
APA
Chicago
ICMJE
MLA
NLM
Fair, R. B., Wortman, J. J., Liu, J., Tischler, M., Masnari, N. A., & Duh, K. Y. (1983). IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices, 30(11), 1584–1585. https://doi.org/10.1109/T-ED.1983.21370
Fair, R. B., J. J. Wortman, J. Liu, M. Tischler, N. A. Masnari, and K. Y. Duh. “IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS.” IEEE Transactions on Electron Devices 30, no. 11 (January 1, 1983): 1584–85. https://doi.org/10.1109/T-ED.1983.21370.
Fair RB, Wortman JJ, Liu J, Tischler M, Masnari NA, Duh KY. IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices. 1983 Jan 1;30(11):1584–5.
Fair, R. B., et al. “IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS.” IEEE Transactions on Electron Devices, vol. 30, no. 11, Jan. 1983, pp. 1584–85. Scopus, doi:10.1109/T-ED.1983.21370.
Fair RB, Wortman JJ, Liu J, Tischler M, Masnari NA, Duh KY. IIIB-8 Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices. 1983 Jan 1;30(11):1584–1585.
Published In
IEEE Transactions on Electron Devices
DOI
EISSN
1557-9646
ISSN
0018-9383
Publication Date
January 1, 1983
Volume
30
Issue
11
Start / End Page
1584 / 1585
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering