A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores
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Wang, J; Tim, Y; Wong, WF; Ong, ZL; Sun, Z; Li, HH
Published in: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC
March 27, 2014
STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 cache architecture that incorporates both SRAM and STT-RAM. The key novelty of the proposal is the exploition of the MESI cache coherence protocol to perform dynamic block reallocation between different cache partitions. Compared to the pure SRAM-based design, our hybrid scheme achieves 38% of energy saving with a mere 0.8% IPC degradation while extending the lifespan of STT-RAM partition at the same time. © 2014 IEEE.
Duke Scholars
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Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC
DOI
Publication Date
March 27, 2014
Start / End Page
610 / 615
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Wang, J., Tim, Y., Wong, W. F., Ong, Z. L., Sun, Z., & Li, H. H. (2014). A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC (pp. 610–615). https://doi.org/10.1109/ASPDAC.2014.6742958
Wang, J., Y. Tim, W. F. Wong, Z. L. Ong, Z. Sun, and H. H. Li. “A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 610–15, 2014. https://doi.org/10.1109/ASPDAC.2014.6742958.
Wang J, Tim Y, Wong WF, Ong ZL, Sun Z, Li HH. A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2014. p. 610–5.
Wang, J., et al. “A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.” Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 2014, pp. 610–15. Scopus, doi:10.1109/ASPDAC.2014.6742958.
Wang J, Tim Y, Wong WF, Ong ZL, Sun Z, Li HH. A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2014. p. 610–615.
Published In
Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC
DOI
Publication Date
March 27, 2014
Start / End Page
610 / 615