Scholars@Duke

• Background
• 

  Education, Training, & Certifications

  • Ph.D., Purdue University 2004
• 

  Previous Appointments & Affiliations

  • Acting Chair of the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2022
  • Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017 - 2020
  • Associate Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2018 - 2020
  • Adjunct Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2016
• Recognition
• 

  In the News

  • JAN 17, 2023

    Office of Faculty Advancement

    Meet Duke’s 2023 Fellows in the ACC Academic Leadership Network

  • SEP 27, 2021

    Duke Engineering News

    Co-Designing Tomorrow's Computers

  • SEP 7, 2021

    Duke Engineering News

    Duke and Pitt Train Enormous AI Models in Health Care, While Protecting Data Privacy

  • MAY 11, 2021

    Duke Engineering News

    Duke Engineers are Using Machine Learning and Radar to Detect Drones in Complex Urban Settings

  • OCT 12, 2020

    Duke Engineering News

    On Security's Frontiers: Trustworthy Computing

  • SEP 17, 2020

    Duke Engineering News

    Duke-Led Team to Develop Privacy-Minded AI Health Learning Platform: NSF Convergence Accelerator Award

  • DEC 23, 2019

    Duke Engineering News

    Detecting Backdoor Attacks on Artificial Neural Networks

  • DEC 13, 2018

    Duke Engineering News

    Hai "Helen" Li Elected a Fellow of the IEEE

  • JAN 3, 2017

    Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain
• 

  Awards & Honors

  • Fellow, Executive Leadership in Academic Technology, Engineering and Science (ELATES). Drexel University. 2022
  • Distinguished Member. Association for Computing Machinery (ACM). 2018
  • Fellow. Institute of Electrical and Electronics Engineers (IEEE). 2018
  • Best Paper Award for the paper titled “Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2017
  • Fulton C. Noss Faculty Fellow. University of Pittsburgh. 2016
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2015
  • Best Paper Award for the paper titled “Quantitative Modeling of Racetrack Memory - A Tradeoff among Area, Performance, and Power”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2015
  • Best Paper Award for the paper titled “A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI). July 2014
  • Best Paper Award for the paper titled “Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems”. Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI). April 2013
  • Air Force Visiting Faculty Research Program (VFRP) Fellowship. AFRL/RIB. 2013
  • DARPA Young Faculty Award. Defense Advanced Research Projects Agency (DARPA). 2013
  • NSF Career Award. National Science Foundation (NSF). 2012
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2011
  • Best Paper Award for the paper titled “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM”. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED). August 2010
  • Best Paper Award for the paper titled “Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)”. the 9th International Symposium on Quality Electronic Design (ISQED). March 2008
• Research
• 

  Selected Grants

  • AI Institute: Athena: AI-Driven Next-generation Networks at the Edge awarded by  National Science Foundation 2021 - 2026
  • CCF Core: Small: Hardware/Software Co-Design for Sustainability at the Edge awarded by  National Science Foundation 2022 - 2025
  • RINGS: A Deep Reinforcement Learning Enabled Large-scale UAV Network with Distributed Navigation, Mobility Control, and Resilience awarded by Ohio State University 2022 - 2025
  • Collaborative Research: ASCENT: 3D memristor convolutional kernels with diffusive memristor based reservoir for real-time machine learning awarded by University of Massachusetts - Amherst 2020 - 2024
  • IUCRC Proposal Phase 1 Duke: Center for Alternative Sustainable and Intelligent Computing (ASIC) awarded by  National Science Foundation 2018 - 2023
  • Collaborative Research: CNS Core: Medium: Exploiting Synergies between Machine learning algorithms and hardware heterogeneity for high-performance and Reliable Manycore Computing Platforms awarded by  National Science Foundation 2020 - 2023
  • Multi-agent Collaborative Learning and Inference at the Edge awarded by Georgia State University 2022 - 2023
  • Track D: The Community Resource for Innovation in Polymer Technology (CRIPT) awarded by Massachusetts Institute of Technology 2021 - 2022
  • FET: Small:RESONANCE:Accelerating Speech/Language Processing through Collective Training using Commodity ReRAM Chips awarded by  National Science Foundation 2019 - 2022
  • A Hardware and Software Co-design Framework for Energy Efficient Neuromorphic Systems awarded by Department of Energy 2020 - 2022
  • SPX: Collaborative Research: Ula! - An Integrated DNN Acceleration Framework with Enhanced Unsupervised Learning Capability awarded by  National Science Foundation 2017 - 2022
  • NSF Convergence Accelerator Track D: A Trusted Integrative Model and Data Sharing Platform for Accelerating AI-Driven Health Innovation awarded by  National Science Foundation 2020 - 2022
  • Neural-Network Enhanced Radar Surveillance (NNERS) awarded by Defense Advanced Research Projects Agency 2020 - 2022
  • The Controller Design and Integration of Memristor-based Neuromorphic System awarded by Air Force Research Laboratory 2018 - 2021
  • Quantifying Ensemble Diversity for Robust Machine Learning (QED RML) awarded by Radiance Technologies, Inc. 2019 - 2021
  • CSR: SMALL: Collaborative Research: GAMBIT: Efficient Graph Processing on a Memristor-based Embedded Computing Platform awarded by  National Science Foundation 2017 - 2020
  • Scalable Event-driven Neuromorphic Learning Mechanics for Human-centric Computing awarded by Intel Corporation 2017 - 2020
  • Reverse Engineering of Deceptions (RED) awarded by Radiance Technologies, Inc. 2019 - 2020
  • SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms awarded by Department of Energy 2017 - 2020
  • Systematically Studying Backdoor Attacks on DNNs and Developing a Detection Architecture awarded by Army Research Office 2019
  • SHF:Small: Cross-Platform Solutions for Pruning and Accelerating Neural Models awarded by  National Science Foundation 2017 - 2019
  • NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains awarded by  National Science Foundation 2017 - 2018
  • Planning IUCRC Duke University: Center for Alternative Sustainable and Intelligent Computing awarded by  National Science Foundation 2017 - 2018
  • The Design of Neuromorphic Controller System Built with Memristor Crossbars awarded by University of Pittsburgh 2017
• 

  External Relationships

  • Aicadium
  • City University of Hong Kong
  • Design Automation Conference (DAC)
  • IEEE IEDM conference
  • King Abdullah University of Science and Technology (KAUST)
  • NYU Abu Dhabi
  • Nanomatronix, LLC
  • Nanyang Technological University, Singapore
  • National Tsing Hua University, Taiwan
  • The Implementation Group (TIG)
  • iSES symposium
• Publications & Artistic Works
• 

  Selected Publications

  • Books

    • Li, H., and Y. Chen. Nonvolatile memory design: Magnetic, resistive, and phase change, 2017. https://doi.org/10.1201/b11354.
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  • Academic Articles

    • Augustine, Charles, and Helen Li. “ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19 (Accepted).” Ieee Design &Amp; Test 40, no. 1 (February 2023): 105–7. https://doi.org/10.1109/mdat.2022.3208552.
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    • Li, Hai Helen. “MWSCAS Guest Editorial Special Issue Based on the 64th International Midwest Symposium on Circuits and Systems.” Ieee Transactions on Circuits and Systems I: Regular Papers 70, no. 1 (January 2023): 1–2. https://doi.org/10.1109/tcsi.2022.3226647.
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    • Li, Ziru, Qilin Zheng, Yiran Chen, and Hai Li. “SpikeSen: Low-latency In-sensor-intelligence Design with Neuromorphic Spiking Neurons.” Ieee Transactions on Circuits and Systems Ii: Express Briefs, 2023, 1–1. https://doi.org/10.1109/tcsii.2023.3235888.
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    • Shafique, M., T. Theocharides, H. Li, and C. Jason Xue. “Introduction to the Special Issue on Accelerating AI on the Edge - Part 2.” Acm Transactions on Embedded Computing Systems 21, no. 6 (December 12, 2022). https://doi.org/10.1145/3563127.
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    • Li, H. H. “Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2022.” Ieee Transactions on Circuits and Systems I: Regular Papers 69, no. 12 (December 1, 2022): 4730. https://doi.org/10.1109/TCSI.2022.3219319.
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    • Ogbogu, C., A. I. Arka, B. K. Joardar, J. R. Doppa, H. Li, K. Chakrabarty, and P. P. Pande. “Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 41, no. 11 (November 1, 2022): 3626–37. https://doi.org/10.1109/TCAD.2022.3197342.
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    • Mao, J., Q. Yang, A. Li, K. W. Nixon, H. Li, and Y. Chen. “Toward Efficient and Adaptive Design of Video Detection System with Deep Neural Networks.” Acm Transactions on Embedded Computing Systems 21, no. 3 (May 1, 2022). https://doi.org/10.1145/3484946.
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    • Li, H. H., A. R. Alameldeen, and O. Mutlu. “Guest Editors' Introduction: Near-Memory and In-Memory Processing.” Ieee Design and Test 39, no. 2 (April 1, 2022): 46–47. https://doi.org/10.1109/MDAT.2021.3124742.
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    • Hanson, E., S. Li, X. Qian, H. Li, and Y. Chen. “DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs.” Ieee Transactions on Computers, January 1, 2022. https://doi.org/10.1109/TC.2022.3184272.
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    • Joardar, B. K., J. R. Doppa, H. Li, K. Chakrabarty, and P. P. Pande. “ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs.” Ieee Transactions on Emerging Topics in Computing, January 1, 2022. https://doi.org/10.1109/TETC.2022.3223630.
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    • Yang, X., H. Yang, J. R. Doppa, P. P. Pande, K. Chakrabarty, and H. Li. “ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-aware ReRAM-based In-Memory Training Systems.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, January 1, 2022. https://doi.org/10.1109/TCAD.2022.3216546.
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    • Joardar, Biresh Kumar, Janardhan Rao Doppa, Hai Li, Krishnendu Chakrabarty, and Partha Pratim Pande. “Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators.” Acm Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–23. https://doi.org/10.1145/3476986.
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    • Yang, Q., J. Mao, Z. Wang, and L. Hai. “Dynamic Regularization on Activation Sparsity for Neural Network Efficiency Improvement.” Acm Journal on Emerging Technologies in Computing Systems 17, no. 4 (October 1, 2021). https://doi.org/10.1145/3447776.
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    • Mao, J., H. Yang, A. Li, H. Li, and Y. Chen. “TPrune: Efficient Transformer Pruning for Mobile Devices.” Acm Transactions on Cyber Physical Systems 5, no. 3 (July 1, 2021). https://doi.org/10.1145/3446640.
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    • Hu, W., C. H. Chang, A. Sengupta, S. Bhunia, R. Kastner, and H. Li. “An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 40, no. 6 (June 1, 2021): 1010–38. https://doi.org/10.1109/TCAD.2020.3047976.
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    • Joardar, B. K., J. R. Doppa, P. P. Pande, H. Li, and K. Chakrabarty. “AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 40, no. 5 (May 1, 2021): 971–84. https://doi.org/10.1109/TCAD.2020.3013194.
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    • Kim, B., E. Hanson, and H. Li. “An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks.” Ieee Transactions on Circuits and Systems Ii: Express Briefs 68, no. 5 (May 1, 2021): 1600–1604. https://doi.org/10.1109/TCSII.2021.3067840.
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    • Yang, Q., and H. Li. “BitSystolic: A 26.7 TOPS/W 2b8b NPU with Configurable Data Flows for Edge Devices.” Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 3 (March 1, 2021): 1134–45. https://doi.org/10.1109/TCSI.2020.3043778.
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    • Liang, F., Z. Tian, M. Dong, S. Cheng, L. Sun, H. Li, Y. Chen, and G. Zhang. “Efficient neural network using pointwise convolution kernels with linear phase constraint.” Neurocomputing 423 (January 29, 2021): 572–79. https://doi.org/10.1016/j.neucom.2020.10.067.
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    • Liu, X., M. Mao, X. Bi, H. Li, and Y. Chen. “Exploring Applications of STT-RAM in GPU Architectures.” Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (January 1, 2021): 238–49. https://doi.org/10.1109/TCSI.2020.3031895.
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    • Lan, Y., K. W. Nixon, Q. Guo, G. Zhang, Y. Xu, H. Li, and Y. Chen. “FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 12 (December 1, 2020): 4791–4804. https://doi.org/10.1109/TCAD.2020.2969982.
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    • Li, Z., B. Li, Z. Fan, and H. Li. “RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 12 (December 1, 2020): 4736–47. https://doi.org/10.1109/TCAD.2020.2981055.
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    • Serrano-Gotarredona, T., M. Valle, F. Conti, and H. Li. “Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020).” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 10, no. 4 (December 1, 2020): 403–5. https://doi.org/10.1109/JETCAS.2020.3040581.
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    • Kurshan, E., H. Li, M. Seok, and Y. Xie. “A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications.” International Journal of Semantic Computing 14, no. 4 (December 1, 2020): 457–75. https://doi.org/10.1142/S1793351X20500063.
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    • Yang, C., B. Liu, H. Li, Y. Chen, M. Barnell, Q. Wu, W. Wen, and J. Rajendran. “Thwarting Replication Attack against Memristor-Based Neuromorphic Computing System.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 10 (October 1, 2020): 2192–2205. https://doi.org/10.1109/TCAD.2019.2937817.
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    • Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, and H. Li. “Adversarial Attack: A New Threat to Smart Devices and How to Defend It.” Ieee Consumer Electronics Magazine 9, no. 4 (July 1, 2020): 49–55. https://doi.org/10.1109/MCE.2020.2969150.
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    • Zhang, G., B. Li, J. Wu, R. Wang, Y. Lan, L. Sun, S. Lei, H. Li, and Y. Chen. “A low-cost and high-speed hardware implementation of spiking neural network.” Neurocomputing 382 (March 21, 2020): 106–15. https://doi.org/10.1016/j.neucom.2019.11.045.
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    • Li, B., J. R. Doppa, P. P. Pande, K. Chakrabarty, J. X. Qiu, and H. H. Li. “3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.” Acm Journal on Emerging Technologies in Computing Systems 16, no. 2 (January 29, 2020). https://doi.org/10.1145/3375699.
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    • Li, B., M. Mao, X. Liu, T. Liu, Z. Liu, W. Wen, Y. Chen, and H. H. Li. “Thread batching for high-performance energy-efficient GPU memory design.” Acm Journal on Emerging Technologies in Computing Systems 15, no. 4 (December 1, 2019). https://doi.org/10.1145/3330152.
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    • Yan, Bonan, Bing Li, Ximing Qiao, Cheng-Xin Xue, Meng‐Fan Chang, Yiran Chen, and Hai Helen Li. “Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives.” Advanced Intelligent Systems 1, no. 7 (November 2019): 1900068–1900068. https://doi.org/10.1002/aisy.201900068.
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    • Yang, J., X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. “Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 38, no. 1 (January 1, 2019): 57–69. https://doi.org/10.1109/TCAD.2018.2802870.
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    • James, A. P., K. N. Salama, H. Li, D. Biolek, G. Indiveri, and L. O. Chua. “Guest Editorial: Special Issue on Large-Scale Memristive Systems and Neurochips for Computational Intelligence.” Ieee Transactions on Emerging Topics in Computational Intelligence 2, no. 5 (October 1, 2018): 320–23. https://doi.org/10.1109/TETCI.2018.2867375.
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    • Wang, D., L. Ma, M. Zhang, J. An, H. H. Li, and Y. Chen. “Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.” Journal of Circuits, Systems and Computers 27, no. 5 (May 1, 2018). https://doi.org/10.1142/S0218126618500810.
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    • Zhang, L., W. Song, J. J. Yang, H. Li, and Y. Chen. “A compact model for selectors based on metal doped electrolyte.” Applied Physics A: Materials Science and Processing 124, no. 4 (April 1, 2018). https://doi.org/10.1007/s00339-018-1706-2.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, M. Albrecht, A. Amoroso, F. F. An, Q. An, et al. “Measurement of e+e−→π0π0ψ(3686) at s from 4.009 to 4.600 GeV and observation of a neutral charmoniumlike structure.” Physical Review D 97, no. 5 (March 7, 2018). https://doi.org/10.1103/physrevd.97.052001.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, O. Albayrak, M. Albrecht, M. Alekseev, D. J. Ambrose, et al. “Study of η(1475) and X(1835) in radiative J/ψ decays to γϕ.” Physical Review D 97, no. 5 (March 6, 2018). https://doi.org/10.1103/physrevd.97.051101.
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    • Basu, A., J. Acharya, T. Karnik, H. Liu, H. Li, J. S. Seo, and C. Song. “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 1 (March 1, 2018): 6–27. https://doi.org/10.1109/JETCAS.2018.2816339.
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    • Chen, Y., H. Li, C. Wu, C. Song, S. Li, C. Min, H. P. Cheng, W. Wen, and X. Liu. “Neuromorphic computing's yesterday, today, and tomorrow – an evolutional view.” Integration 61 (March 1, 2018): 49–61. https://doi.org/10.1016/j.vlsi.2017.11.001.
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    • Mohanty, S. P., M. Hüebner, C. J. Xue, X. Li, and H. Li. “Guest editorial circuit and system design automation for internet of things.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 1 (January 1, 2018): 3–6. https://doi.org/10.1109/TCAD.2017.2779960.
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    • Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.” Ieee Transactions on Computers 66, no. 9 (September 1, 2017): 1478–90. https://doi.org/10.1109/TC.2017.2690855.
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    • Hu, M., Y. Chen, J. J. Yang, Y. Wang, and H. Li. “A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (August 1, 2017): 1353–66. https://doi.org/10.1109/TCAD.2016.2618866.
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    • Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1167–80. https://doi.org/10.1109/TCAD.2016.2619480.
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    • Bi, X., M. Mao, D. Wang, and H. Li. “Cross-layer optimization for multilevel cell STT-RAM caches.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (June 1, 2017): 1807–20. https://doi.org/10.1109/TVLSI.2017.2665543.
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    • Chen, Y., H. H. Li, I. Bayram, and E. Eken. “Recent Technology Advances of Emerging Memories.” Ieee Design and Test 34, no. 3 (June 1, 2017): 8–22. https://doi.org/10.1109/MDAT.2017.2685381.
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    • Eken, E., I. Bayram, Y. Zhang, B. Yan, H. Li, and Y. Chen. “Giant Spin-Hall assisted STT-RAM and logic design.” Integration, the Vlsi Journal 58 (June 1, 2017): 253–61. https://doi.org/10.1016/j.vlsi.2017.04.002.
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    • Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” Ieee Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.
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    • Li, H. H., Y. Chen, C. Liu, J. P. Strachan, and N. Davila. “Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.” Ieee Consumer Electronics Magazine 6, no. 1 (January 1, 2017): 94–103. https://doi.org/10.1109/MCE.2016.2614523.
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    • Wu, Chunpeng, Hsin‐Pai Cheng, Sicheng Li, Hai Helen Li, and Yiran Chen. “ApesNet: a pixel‐wise efficient segmentation network for embedded devices.” Iet Cyber Physical Systems: Theory &Amp; Applications 1, no. 1 (December 2016): 78–85. https://doi.org/10.1049/iet-cps.2016.0027.
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    • Li, H. H., Q. Qiu, and Y. Wang. “Guest Editorial: Design and Applications of Neuromorphic Computing System.” Ieee Transactions on Multi Scale Computing Systems 2, no. 4 (October 1, 2016): 223–24. https://doi.org/10.1109/TMSCS.2016.2631918.
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    • Qiu, Q., Z. Li, K. Ahmed, W. Liu, S. F. Habib, H. Li, and M. Hu. “A Neuromorphic Architecture for Context Aware Text Image Recognition.” Journal of Signal Processing Systems 84, no. 3 (September 1, 2016): 355–69. https://doi.org/10.1007/s11265-015-1067-4.
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    • Pyle, S. D., H. Li, and R. F. DeMara. “Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device.” Electronics Letters 52, no. 14 (July 7, 2016): 1238–40. https://doi.org/10.1049/el.2015.4114.
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    • Hu, M., Y. Wang, W. Wen, and H. Li. “Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 235–46. https://doi.org/10.1109/JETCAS.2016.2547780.
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    • Yang, J., Z. Sun, X. Wang, Y. Chen, and H. Li. “Spintronic Memristor as Interface between DNA and Solid State Devices.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 212–21. https://doi.org/10.1109/JETCAS.2016.2547700.
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    • Duan, S., Z. Dong, X. Hu, L. Wang, and H. Li. “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.” Neural Computing and Applications 27, no. 4 (May 1, 2016): 837–44. https://doi.org/10.1007/s00521-015-1899-7.
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    • Liu, X., M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, et al. “Harmonica: A Framework of Heterogeneous Computing Systems with Memristor-Based Neuromorphic Computing Accelerators.” Ieee Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 1, 2016): 617–28. https://doi.org/10.1109/TCSI.2016.2529279.
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    • Mao, F., Y. C. Chen, W. Zhang, H. Li, and B. He. “Library-based placement and routing in FPGAs with support of partial reconfiguration.” Acm Transactions on Design Automation of Electronic Systems 21, no. 4 (May 1, 2016). https://doi.org/10.1145/2901295.
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    • Sun, Z., X. Bi, W. Wu, S. Yoo, and H. H. Li. “Array Organization and Data Management Exploration in Racetrack Memory.” Ieee Transactions on Computers 65, no. 4 (April 1, 2016): 1041–54. https://doi.org/10.1109/TC.2014.2360545.
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    • Yang, J., P. Wang, Y. Zhang, Y. Cheng, W. Zhao, Y. Chen, and H. H. Li. “Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 3 (March 1, 2016): 380–93. https://doi.org/10.1109/TCAD.2015.2474366.
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    • Zhang, Y., Y. Li, Z. Sun, H. Li, Y. Chen, and A. K. Jones. “Read performance: The newest barrier in scaled stt-ram.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 23, no. 6 (June 1, 2015): 1170–74. https://doi.org/10.1109/TVLSI.2014.2326797.
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    • Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A novel self-reference technique for STT-RAM read and write reliability enhancement.” Ieee Transactions on Magnetics 50, no. 11 (November 1, 2014). https://doi.org/10.1109/TMAG.2014.2323196.
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    • Hu, Miao, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, and Richard W. Linderman. “Memristor crossbar-based neuromorphic computing system: a case study.” Ieee Transactions on Neural Networks and Learning Systems 25, no. 10 (October 2014): 1864–78. https://doi.org/10.1109/tnnls.2013.2296777.
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    • Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” Thescientificworldjournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.
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    • Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.
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    • Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” Acm Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.
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    • Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.” Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013). https://doi.org/10.1145/2500459.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache.” Acm Transactions on Architecture and Code Optimization 10, no. 4 (January 1, 2013): 1–22. https://doi.org/10.1145/2541228.2555308.
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    • Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” Ieee Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.
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    • Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” Ieee Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.
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    • Li, H. H., and Z. Sun. “Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400085.
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    • Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” Acm Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.
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    • Sun, Z., H. Li, and X. Wang. “Magnetic tunnel junction design margin exploration for self-reference sensing scheme.” Journal of Applied Physics 111, no. 7 (April 2012): 7C726–7263. https://doi.org/10.1063/1.3679647.
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    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme.” Ieee Journal of Solid State Circuits 47, no. 2 (February 1, 2012): 560–73. https://doi.org/10.1109/JSSC.2011.2170778.
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    • Sun, Z., H. Li, Y. Chen, and X. Wang. “Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (January 1, 2012): 2020–30. https://doi.org/10.1109/TVLSI.2011.2166282.
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    • Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity.” Neural Plasticity 2012 (January 2012): 272374. https://doi.org/10.1155/2012/272374.
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    • Dong, X., X. Wu, Y. Xie, Y. Chen, and H. Li. “Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation.” Iet Computers and Digital Techniques 5, no. 3 (May 1, 2011): 213–20. https://doi.org/10.1049/iet-cdt.2009.0091.
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    • Zhu, W., H. Li, Y. Chen, and X. Wang. “Current switching in MgO-based magnetic tunneling junctions.” Ieee Transactions on Magnetics 47, no. 1 PART 2 (January 1, 2011): 156–60. https://doi.org/10.1109/TMAG.2010.2085441.
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    • Hu, M., H. H. Li, Y. Chen, and X. Wang. “Spintronic memristor: Compact model and statistical analysis.” Journal of Low Power Electronics 7, no. 2 (January 1, 2011): 234–44. https://doi.org/10.1166/jolpe.2011.1131.
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    • Li, H., X. Wang, Z. L. Ong, W. F. Wong, Y. Zhang, P. Wang, and Y. Chen. “Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement.” Ieee Transactions on Magnetics 47, no. 10 (January 1, 2011): 2356–59. https://doi.org/10.1109/TMAG.2011.2159262.
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    • Wang, P., X. Wang, Y. Zhang, H. Li, S. P. Levitan, and Y. Chen. “Nonpersistent errors optimization in spin-MOS logic and storage circuitry.” Ieee Transactions on Magnetics 47, no. 10 (January 1, 2011): 3860–63. https://doi.org/10.1109/TMAG.2011.2153838.
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    • Zhang, Y., X. Wang, H. Li, and Y. Chen. “STT-RAM cell optimization considering MTJ and CMOS variations.” Ieee Transactions on Magnetics 47, no. 10 (January 1, 2011): 2962–65. https://doi.org/10.1109/TMAG.2011.2158810.
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    • Chen, Y., X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. “Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (December 1, 2010): 1724–34. https://doi.org/10.1109/TVLSI.2009.2032192.
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    • Chen, Y., W. Tian, H. Li, X. Wang, and W. Zhu. “PCMO device with high switching stability.” Ieee Electron Device Letters 31, no. 8 (August 1, 2010): 866–68. https://doi.org/10.1109/LED.2010.2050457.
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    • Chen, Y., and H. Li. “Patents relevant to cross-point memory array.” Recent Patents on Electrical Engineering 3, no. 2 (June 25, 2010): 114–24. https://doi.org/10.2174/1874476111003020114.
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    • Xi, H., J. Stricklin, H. Li, Y. Chen, X. Wang, Y. Zheng, Z. Gao, and M. X. Tang. “Spin transfer torque memory with thermal assist mechanism: A case study.” Ieee Transactions on Magnetics 46, no. 3 PART 2 (March 1, 2010): 860–65. https://doi.org/10.1109/TMAG.2009.2033674.
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    • Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.
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    • Wang, X., Y. Chen, Y. Gu, and H. Li. “Spintronic memristor temperature sensor.” Ieee Electron Device Letters 31, no. 1 (January 1, 2010): 20–22. https://doi.org/10.1109/LED.2009.2035643.
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    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.
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    • Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.
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    • Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” Ieee Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.
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    • Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” Ieee Transactions on Magnetics 44, no. 11 PART 2 (January 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.
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    • Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.
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    • Li, H., S. Bhunia, Y. Chen, K. Roy, and T. N. Vijaykumar. “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (March 1, 2004): 245–54. https://doi.org/10.1109/TVLSI.2004.824307.
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    • Agarwal, A., H. Li, and K. Roy. “A single-Vt low-leakage gated-ground cache for deep submicron.” Ieee Journal of Solid State Circuits 38, no. 2 (February 1, 2003): 319–28. https://doi.org/10.1109/JSSC.2002.807414.
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  • Book Sections

    • Yeats, E., F. Liu, D. Womble, and H. Li. “NashAE: Disentangling Representations Through Adversarial Covariance Minimization,” 13687 LNCS:36–51, 2022. https://doi.org/10.1007/978-3-031-19812-0_3.
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    • Li, Z., C. Liu, H. Li, and Y. Chen. “Neuromorphic Hardware Acceleration Enabled by Emerging Technologies.” In Emerging Technology and Architecture for Big-Data Analytics. Springer, 2017.
    • Chen, Y. C., Y. Wang, W. Zhang, Y. Chen, and H. H. Li. “In-place logic obfuscation for emerging nonvolatile FPGAs.” In Fundamentals of IP and SoC Security: Design, Verification, and Debug, 277–93, 2017. https://doi.org/10.1007/978-3-319-50057-7_11.
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    • Yang, C., H. Li, and Y. Chen. “Nanoscale memory architectures for neuromorphic computing.” In Security Opportunities in Nano Devices and Emerging Technologies, 215–34, 2017. https://doi.org/10.1201/9781315265056.
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    • Li, H. H., M. Hu, and B. Liu. “Memristor modeling - static, statistical, and stochastic methodologies.” In Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, 313–35, 2016. https://doi.org/10.1049/PBCS029E_ch11.
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    • Zhang, Y., W. Wen, H. Li, and Y. Chen. “The Prospect of STT-RAM Scaling.” In Metallic Spintronic Devices. CRC Press, 2014.
    • Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.
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    • Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.
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    • Li, H., M. Hu, and R. Pino. “Statistical Memristor Model and Its Applications in Neuromorphic Computing.” In Advances in Neuromorphic Memristor Science and Applications, edited by R. Kozma, R. Pino, and G. Pazienza. Springer Science & Business Media, 2012.
    • Chen, Y., H. Li, Y. Xie, and D. Niu. “Low Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing. CRC Press, 2012.
    • Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.

  • Reports

    • Chen, Yiran, and Hai Li. “SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms.” Office of Scientific and Technical Information (OSTI), February 26, 2022. https://doi.org/10.2172/1846568.
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  • Conference Papers

    • Hanson, E., S. Li, H. H. Li, and Y. Chen. “Cascading Structured Pruning: Enabling High Data Reuse for Sparse DNN Accelerators.” In Proceedings  International Symposium on Computer Architecture, 522–35, 2022. https://doi.org/10.1145/3470496.3527419.
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    • Fang, H., B. Taylor, Z. Li, Z. Mei, H. H. Li, and Q. Qiu. “Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning.” In Proceedings  Design Automation Conference, 2021-December:361–66, 2021. https://doi.org/10.1109/DAC18074.2021.9586133.
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    • Li, S., E. Hanson, X. Qian, H. H. Li, and Y. Chen. “ESCALATE: Boosting the efficiency of sparse CNN accelerator with kernel decomposition.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 992–1004, 2021. https://doi.org/10.1145/3466752.3480043.
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    • Wang, B., J. Guo, A. Li, Y. Chen, and H. Li. “Privacy-Preserving Representation Learning on Graphs: A Mutual Information Perspective.” In Proceedings of the Acm Sigkdd International Conference on Knowledge Discovery and Data Mining, 1667–76, 2021. https://doi.org/10.1145/3447548.3467273.
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    • Yang, C., L. Ding, Y. Chen, and H. Li. “Defending against GAN-based DeepFake Attacks via Transformation-aware Adversarial Faces.” In Proceedings of the International Joint Conference on Neural Networks, Vol. 2021-July, 2021. https://doi.org/10.1109/IJCNN52387.2021.9533868.
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    • Zhang, J., Y. Huang, H. Yang, M. Martinez, G. Hickman, J. Krolik, and H. Li. “Efficient FPGA Implementation of a Convolutional Neural Network for Radar Signal Processing.” In 2021 Ieee 3rd International Conference on Artificial Intelligence Circuits and Systems, Aicas 2021, 2021. https://doi.org/10.1109/AICAS51828.2021.9458573.
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    • Chen, F., L. Song, H. H. Li, and Y. Chen. “RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification.” In Proceedings  Design, Automation and Test in Europe, Date, 2021-February:340–43, 2021. https://doi.org/10.23919/DATE51398.2021.9473993.
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    • Chen, F., L. Song, H. Li, and Y. Chen. “Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D.” In Proceedings  Design, Automation and Test in Europe, Date, 2021-February:1240–45, 2021. https://doi.org/10.23919/DATE51398.2021.9474208.
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    • Ma, W., G. Xie, R. Li, W. Liu, H. H. Li, and W. Chang. “Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality.” In Proceedings  Design, Automation and Test in Europe, Date, 2021-February:1899–1904, 2021. https://doi.org/10.23919/DATE51398.2021.9473962.
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    • Zhang, G. L., B. Li, X. Huang, C. Shen, S. Zhang, F. Burcea, H. Graeb, T. Y. Ho, H. Li, and U. Schlichtmann. “An Efficient Programming Framework for Memristor-based Neuromorphic Computing.” In Proceedings  Design, Automation and Test in Europe, Date, 2021-February:1068–73, 2021. https://doi.org/10.23919/DATE51398.2021.9474084.
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    • Zhang, S., H. H. Li, and U. Schlichtmann. “Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 107–13, 2021. https://doi.org/10.1145/3394885.3431523.
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    • Cheng, H. P., T. Zhang, Y. Zhang, S. Li, F. Liang, F. Yan, M. Li, V. Chandra, H. Li, and Y. Chen. “NASGEM: Neural Architecture Search via Graph Embedding Method.” In 35th Aaai Conference on Artificial Intelligence, Aaai 2021, 8B:7090–98, 2021.
    • Sun, J., A. Li, B. Wang, H. Yang, H. Li, and Y. Chen. “Soteria: Provable Defense against Privacy Leakage in Federated Learning from Representation Perspective.” In Proceedings of the Ieee Computer Society Conference on Computer Vision and Pattern Recognition, 9307–15, 2021. https://doi.org/10.1109/CVPR46437.2021.00919.
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    • Taylor, B., A. Shrestha, Q. Qiu, and H. Li. “1S1R-based stable learning through single-spike-encoded spike-timing-dependent plasticity.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2021-May, 2021. https://doi.org/10.1109/ISCAS51556.2021.9401644.
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    • Wang, Y., Z. Zhu, F. Chen, M. Ma, G. Dai, H. Li, and Y. Chen. “REREC: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2021-November, 2021. https://doi.org/10.1109/ICCAD51958.2021.9643573.
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    • Yang, X., S. Belakaria, B. K. Joardar, H. Yang, J. R. Doppa, P. P. Pande, K. Chakrabarty, and H. Li. “Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2021-November, 2021. https://doi.org/10.1109/ICCAD51958.2021.9643444.
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    • Yeats, Eric, Yiran Chen, and Hai Li. “Improving Gradient Regularization using Complex-Valued Neural Networks.” In International Conference on Machine Learning, Vol 139, Vol. 139, 2021.
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    • Zhang, Qian, Bo Wang, Wei Wen, Hai Li, and Junhui Liu. “Line Art Correlation Matching Feature Transfer Network for Automatic Animation Colorization.” In 2021 Ieee Winter Conference on Applications of Computer Vision (Wacv). IEEE, 2021. https://doi.org/10.1109/wacv48630.2021.00392.
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    • Zhang, S., H. Li, and U. Schlichtmann. “Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2021-November, 2021. https://doi.org/10.1109/ICCAD51958.2021.9643588.
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    • Xie, Z., H. Li, X. Xu, J. Hu, and Y. Chen. “Fast IR Drop Estimation with Machine Learning : Invited Paper.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2020-November, 2020. https://doi.org/10.1145/3400302.3415763.
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    • Yang, X., B. Yan, H. Li, and Y. Chen. “ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2020-November, 2020. https://doi.org/10.1145/3400302.3415640.
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    • Zheng, Q., X. Li, Z. Wang, G. Sun, Y. Cai, R. Huang, Y. Chen, and H. Li. “MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2020-November, 2020. https://doi.org/10.1145/3400302.3415666.
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    • Wen, W., F. Yan, Y. Chen, and H. Li. “AutoGrow: Automatic Layer Growing in Deep Convolutional Networks.” In Proceedings of the Acm Sigkdd International Conference on Knowledge Discovery and Data Mining, 833–41, 2020. https://doi.org/10.1145/3394486.3403126.
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    • Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.” In Proceedings  2020 Ieee International Conference on Artificial Intelligence Circuits and Systems, Aicas 2020, 11–15, 2020. https://doi.org/10.1109/AICAS48895.2020.9073995.
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    • Kim, B., and H. Li. “Leveraging 3D vertical RRAM to developing neuromorphic architecture for pattern classification.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2020-July:258–63, 2020. https://doi.org/10.1109/ISVLSI49217.2020.00054.
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    • Li, Z., B. Yan, and H. H. Li. “ReSiPE: ReRAM-based single-spiking processing-in-memory engine.” In Proceedings  Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218578.
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    • Zheng, Q., Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. L. Yang, and H. H. Li. “Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks.” In Proceedings  Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218590.
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    • Wu, C., B. Ni, and H. Li. “Redistributing and Re-Stylizing Features for Training a Fast Photorealistic Stylizer.” In Proceedings of the International Joint Conference on Neural Networks, 2020. https://doi.org/10.1109/IJCNN48605.2020.9207095.
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    • Wu, C., and H. Li. “Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-Quality Data for Training.” In Proceedings of the International Joint Conference on Neural Networks, 2020. https://doi.org/10.1109/IJCNN48605.2020.9207546.
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    • Yang, H., M. Tang, W. Wen, F. Yan, D. Hu, A. Li, H. Li, and Y. Chen. “Learning low-rank deep neural networks via singular vector orthogonality regularization and singular value sparsification.” In Ieee Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2020-June:2899–2908, 2020. https://doi.org/10.1109/CVPRW50498.2020.00347.
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    • Zhang, J., J. Huang, M. Deisher, H. Li, and Y. Chen. “Structural sparsification for far-field speaker recognition with intel R GNA.” In Icassp, Ieee International Conference on Acoustics, Speech and Signal Processing  Proceedings, 2020-May:3037–41, 2020. https://doi.org/10.1109/ICASSP40776.2020.9054569.
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    • Wang, Y., F. Chen, L. Song, C. J. Richard Shi, H. H. Li, and Y. Chen. “ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1472–77, 2020. https://doi.org/10.23919/DATE48585.2020.9116422.
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    • Joardar, B. K., N. Kannappan Jayakodi, J. R. Doppa, H. Li, P. P. Pande, and K. Chakrabarty. “GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 228–33, 2020. https://doi.org/10.23919/DATE48585.2020.9116273.
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    • Zhang, S., B. Li, H. H. Li, and U. Schlichtmann. “A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1426–31, 2020. https://doi.org/10.23919/DATE48585.2020.9116323.
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    • Chen, F., L. Song, H. H. Li, and Y. Chen. “PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2020-January:175–80, 2020. https://doi.org/10.1109/ASP-DAC47756.2020.9045555.
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    • Li, S., E. Hanson, H. Li, and Y. Chen. “PENNI: Pruned kernel sharing for efficient cnn inference.” In 37th International Conference on Machine Learning, Icml 2020, PartF168147-8:5819–29, 2020.
    • Song, L., F. Chen, Y. Chen, and H. H. Li. “Parallelism in Deep Learning Accelerators.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2020-January:645–50, 2020. https://doi.org/10.1109/ASP-DAC47756.2020.9045206.
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    • Zhang, T., H. P. Cheng, Z. Li, F. Yan, C. Huang, H. Li, and Y. Chen. “AutoShrink: A topology-aware NAS for discovering efficient neural architecture.” In Aaai 2020  34th Aaai Conference on Artificial Intelligence, 6829–36, 2020.
    • Taylor, B., Z. Li, B. Yan, H. Li, and Y. Chen. “Highly efficient neuromorphic computing systems with emerging nonvolatile memories.” In Proceedings of Spie  the International Society for Optical Engineering, Vol. 11324, 2020. https://doi.org/10.1117/12.2554915.
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    • Yan, B., M. Liu, Y. Chen, K. Chakrabarty, and H. Li. “On Designing Efficient and Reliable Nonvolatile Memory-Based Computing-In-Memory Accelerators.” In Technical Digest  International Electron Devices Meeting, Iedm, Vol. 2019-December, 2019. https://doi.org/10.1109/IEDM19573.2019.8993562.
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    • Li, H., Y. Chen, K. Roy, and C. K. Koh. “SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2006:158–63, 2006.
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    • Chen, Y. R., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Cicc: Proceedings of the Ieee 2005 Custom Integrated Circuits Conference, 775–78. IEEE, 2005.
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