Scholars@Duke

• Background
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  Education, Training, & Certifications

  • Ph.D., Purdue University 2004
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  Duke Appointment History

  • Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017 - 2020
  • Associate Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2018 - 2020
  • Adjunct Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2016
• Recognition
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  In the News

  • JAN 3, 2017

    Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain
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  Awards & Honors

  • Best Paper Award for the paper titled “Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2017
  • Fulton C. Noss Faculty Fellow. University of Pittsburgh. 2016
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2015
  • Best Paper Award for the paper titled “Quantitative Modeling of Racetrack Memory - A Tradeoff among Area, Performance, and Power”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2015
  • Best Paper Award for the paper titled “A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI). July 2014
  • Best Paper Award for the paper titled “Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems”. Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI). April 2013
  • Air Force Visiting Faculty Research Program (VFRP) Fellowship. AFRL/RIB. 2013
  • DARPA Young Faculty Award. Defense Advanced Research Projects Agency (DARPA). 2013
  • NSF Career Award. National Science Foundation (NSF). 2012
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2011
  • Best Paper Award for the paper titled “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM”. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED). August 2010
  • Best Paper Award for the paper titled “Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)”. the 9th International Symposium on Quality Electronic Design (ISQED). March 2008
• Research
• 

  Selected Grants

  • IUCRC Proposal Phase 1 Duke: Center for Alternative Sustainable and Intelligent Computing (ASIC) awarded by  National Science Foundation 2018 - 2023
  • Collaborative Research: CNS Core: Medium: Exploiting Synergies between Machine learning algorithms and hardware heterogeneity for high-performance and Reliable Manycore Computing Platforms awarded by  National Science Foundation 2020 - 2023
  • FET: Small:RESONANCE:Accelerating Speech/Language Processing through Collective Training using Commodity ReRAM Chips awarded by  National Science Foundation 2019 - 2022
  • Neural-Network Enhanced Radar Surveillance (NNERS) awarded by Defense Advanced Research Projects Agency 2020 - 2021
  • SPX: Collaborative Research: Ula! - An Integrated DNN Acceleration Framework with Enhanced Unsupervised Learning Capability awarded by  National Science Foundation 2017 - 2021
  • The Controller Design and Integration of Memristor-based Neuromorphic System awarded by Air Force Research Laboratory 2018 - 2021
  • NSF Convergence Accelerator Track D: A Trusted Integrative Model and Data Sharing Platform for Accelerating AI-Driven Health Innovation awarded by  National Science Foundation 2020 - 2021
  • CSR: SMALL: Collaborative Research: GAMBIT: Efficient Graph Processing on a Memristor-based Embedded Computing Platform awarded by  National Science Foundation 2017 - 2020
  • Scalable Event-driven Neuromorphic Learning Mechanics for Human-centric Computing awarded by Intel Corporation 2017 - 2020
  • Quantifying Ensemble Diversity for Robust Machine Learning (QED RML) awarded by Radiance Technologies, Inc. 2019 - 2020
  • SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms awarded by Department of Energy 2017 - 2020
  • Systematically Studying Backdoor Attacks on DNNs and Developing a Detection Architecture awarded by Army Research Office 2019
  • SHF:Small: Cross-Platform Solutions for Pruning and Accelerating Neural Models awarded by  National Science Foundation 2017 - 2019
  • NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains awarded by  National Science Foundation 2017 - 2018
  • Planning IUCRC Duke University: Center for Alternative Sustainable and Intelligent Computing awarded by  National Science Foundation 2017 - 2018
  • The Design of Neuromorphic Controller System Built with Memristor Crossbars awarded by University of Pittsburgh 2017
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  External Relationships

  • Nanomatronix, LLC
  • NeoNexus Pte. Ltd.
  • Technische University M¿nchen
• Publications & Artistic Works
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  Selected Publications

  • Books

    • Li, H., and Y. Chen. Nonvolatile memory design: Magnetic, resistive, and phase change, 2017. https://doi.org/10.1201/b11354.
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  • Academic Articles

    • Li, B., J. R. Doppa, P. P. Pande, K. Chakrabarty, J. X. Qiu, and H. H. Li. “3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.” Acm Journal on Emerging Technologies in Computing Systems 16, no. 2 (January 29, 2020). https://doi.org/10.1145/3375699.
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    • Li, B., M. Mao, X. Liu, T. Liu, Z. Liu, W. Wen, Y. Chen, and H. H. Li. “Thread batching for high-performance energy-efficient GPU memory design.” Acm Journal on Emerging Technologies in Computing Systems 15, no. 4 (December 1, 2019). https://doi.org/10.1145/3330152.
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    • Yang, J., X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. “Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 38, no. 1 (January 1, 2019): 57–69. https://doi.org/10.1109/TCAD.2018.2802870.
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    • Wang, D., L. Ma, M. Zhang, J. An, H. H. Li, and Y. Chen. “Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.” Journal of Circuits, Systems and Computers 27, no. 5 (May 1, 2018). https://doi.org/10.1142/S0218126618500810.
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    • Zhang, L., W. Song, J. J. Yang, H. Li, and Y. Chen. “A compact model for selectors based on metal doped electrolyte.” Applied Physics A: Materials Science and Processing 124, no. 4 (April 1, 2018). https://doi.org/10.1007/s00339-018-1706-2.
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    • Basu, A., J. Acharya, T. Karnik, H. Liu, H. Li, J. S. Seo, and C. Song. “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 1 (March 1, 2018): 6–27. https://doi.org/10.1109/JETCAS.2018.2816339.
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    • Chen, Y., H. Li, C. Wu, C. Song, S. Li, C. Min, H. P. Cheng, W. Wen, and X. Liu. “Neuromorphic computing's yesterday, today, and tomorrow – an evolutional view.” Integration 61 (March 1, 2018): 49–61. https://doi.org/10.1016/j.vlsi.2017.11.001.
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    • Mohanty, S. P., M. Hüebner, C. J. Xue, X. Li, and H. Li. “Guest editorial circuit and system design automation for internet of things.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 1 (January 1, 2018): 3–6. https://doi.org/10.1109/TCAD.2017.2779960.
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    • Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.” Ieee Transactions on Computers 66, no. 9 (September 1, 2017): 1478–90. https://doi.org/10.1109/TC.2017.2690855.
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    • Hu, M., Y. Chen, J. J. Yang, Y. Wang, and H. Li. “A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (August 1, 2017): 1353–66. https://doi.org/10.1109/TCAD.2016.2618866.
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    • Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1167–80. https://doi.org/10.1109/TCAD.2016.2619480.
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    • Bi, X., M. Mao, D. Wang, and H. Li. “Cross-layer optimization for multilevel cell STT-RAM caches.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (June 1, 2017): 1807–20. https://doi.org/10.1109/TVLSI.2017.2665543.
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    • Chen, Y., H. H. Li, I. Bayram, and E. Eken. “Recent Technology Advances of Emerging Memories.” Ieee Design and Test 34, no. 3 (June 1, 2017): 8–22. https://doi.org/10.1109/MDAT.2017.2685381.
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    • Eken, E., I. Bayram, Y. Zhang, B. Yan, H. Li, and Y. Chen. “Giant Spin-Hall assisted STT-RAM and logic design.” Integration, the Vlsi Journal 58 (June 1, 2017): 253–61. https://doi.org/10.1016/j.vlsi.2017.04.002.
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    • Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” Ieee Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.
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    • Li, H. H., Y. Chen, C. Liu, J. P. Strachan, and N. Davila. “Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.” Ieee Consumer Electronics Magazine 6, no. 1 (January 1, 2017): 94–103. https://doi.org/10.1109/MCE.2016.2614523.
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    • Wu, Chunpeng, Hsin-Pai Cheng, Sicheng Li, Hai Helen Li, and Yiran Chen. “ApesNet: a pixel-wise efficient segmentation network for embedded devices.” Iet Cyber Physical Systems: Theory & Applications 1, no. 1 (December 1, 2016): 78–85. https://doi.org/10.1049/iet-cps.2016.0027.
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    • Li, H. H., Q. Qiu, and Y. Wang. “Guest Editorial: Design and Applications of Neuromorphic Computing System.” Ieee Transactions on Multi Scale Computing Systems 2, no. 4 (October 1, 2016): 223–24. https://doi.org/10.1109/TMSCS.2016.2631918.
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    • Qiu, Q., Z. Li, K. Ahmed, W. Liu, S. F. Habib, H. Li, and M. Hu. “A Neuromorphic Architecture for Context Aware Text Image Recognition.” Journal of Signal Processing Systems 84, no. 3 (September 1, 2016): 355–69. https://doi.org/10.1007/s11265-015-1067-4.
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    • Pyle, S. D., H. Li, and R. F. DeMara. “Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device.” Electronics Letters 52, no. 14 (July 7, 2016): 1238–40. https://doi.org/10.1049/el.2015.4114.
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    • Hu, M., Y. Wang, W. Wen, and H. Li. “Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 235–46. https://doi.org/10.1109/JETCAS.2016.2547780.
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    • Yang, J., Z. Sun, X. Wang, Y. Chen, and H. Li. “Spintronic Memristor as Interface between DNA and Solid State Devices.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 212–21. https://doi.org/10.1109/JETCAS.2016.2547700.
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    • Duan, S., Z. Dong, X. Hu, L. Wang, and H. Li. “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.” Neural Computing and Applications 27, no. 4 (May 1, 2016): 837–44. https://doi.org/10.1007/s00521-015-1899-7.
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    • Liu, X., M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, et al. “Harmonica: A Framework of Heterogeneous Computing Systems with Memristor-Based Neuromorphic Computing Accelerators.” Ieee Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 1, 2016): 617–28. https://doi.org/10.1109/TCSI.2016.2529279.
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    • Mao, F., Y. C. Chen, W. Zhang, H. Li, and B. He. “Library-based placement and routing in FPGAs with support of partial reconfiguration.” Acm Transactions on Design Automation of Electronic Systems 21, no. 4 (May 1, 2016). https://doi.org/10.1145/2901295.
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    • Sun, Z., X. Bi, W. Wu, S. Yoo, and H. H. Li. “Array Organization and Data Management Exploration in Racetrack Memory.” Ieee Transactions on Computers 65, no. 4 (April 1, 2016): 1041–54. https://doi.org/10.1109/TC.2014.2360545.
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    • Yang, J., P. Wang, Y. Zhang, Y. Cheng, W. Zhao, Y. Chen, and H. H. Li. “Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 3 (March 1, 2016): 380–93. https://doi.org/10.1109/TCAD.2015.2474366.
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    • Zhang, Y., Y. Li, Z. Sun, H. Li, Y. Chen, and A. K. Jones. “Read performance: The newest barrier in scaled stt-ram.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 23, no. 6 (June 1, 2015): 1170–74. https://doi.org/10.1109/TVLSI.2014.2326797.
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    • Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A novel self-reference technique for STT-RAM read and write reliability enhancement.” Ieee Transactions on Magnetics 50, no. 11 (November 1, 2014). https://doi.org/10.1109/TMAG.2014.2323196.
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    • Hu, Miao, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, and Richard W. Linderman. “Memristor crossbar-based neuromorphic computing system: a case study.” Ieee Transactions on Neural Networks and Learning Systems 25, no. 10 (October 2014): 1864–78. https://doi.org/10.1109/tnnls.2013.2296777.
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    • Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” Thescientificworldjournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.
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    • Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.
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    • Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” Acm Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.
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    • Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.” Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013). https://doi.org/10.1145/2500459.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache.” Acm Transactions on Architecture and Code Optimization 10, no. 4 (January 1, 2013): 1–22. https://doi.org/10.1145/2541228.2555308.
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    • Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” Ieee Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.
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    • Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” Ieee Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.
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    • LI, HAI H. E. L. E. N., and Z. H. E. N. Y. U. SUN. “VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT.” Spin 02, no. 03 (September 2012): 1240008–1240008. https://doi.org/10.1142/s2010324712400085.
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    • Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” Acm Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.
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    • Sun, Z., H. Li, and X. Wang. “Magnetic tunnel junction design margin exploration for self-reference sensing scheme.” Journal of Applied Physics 111, no. 7 (April 2012): 7C726–7263. https://doi.org/10.1063/1.3679647.
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    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme.” Ieee Journal of Solid State Circuits 47, no. 2 (February 1, 2012): 560–73. https://doi.org/10.1109/JSSC.2011.2170778.
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    • Sun, Z., H. Li, Y. Chen, and X. Wang. “Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (January 1, 2012): 2020–30. https://doi.org/10.1109/TVLSI.2011.2166282.
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    • Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity.” Neural Plasticity 2012 (January 2012): 272374. https://doi.org/10.1155/2012/272374.
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    • Li, H., X. Wang, Z. L. Ong, W. F. Wong, Y. Zhang, P. Wang, and Y. Chen. “Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2356–59. https://doi.org/10.1109/TMAG.2011.2159262.
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    • Wang, P., X. Wang, Y. Zhang, H. Li, S. P. Levitan, and Y. Chen. “Nonpersistent errors optimization in spin-MOS logic and storage circuitry.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 3860–63. https://doi.org/10.1109/TMAG.2011.2153838.
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    • Zhang, Y., X. Wang, H. Li, and Y. Chen. “STT-RAM cell optimization considering MTJ and CMOS variations.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2962–65. https://doi.org/10.1109/TMAG.2011.2158810.
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    • Dong, X., X. Wu, Y. Xie, Y. Chen, and H. Li. “Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation.” Iet Computers and Digital Techniques 5, no. 3 (May 1, 2011): 213–20. https://doi.org/10.1049/iet-cdt.2009.0091.
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    • Hu, M., H. H. Li, Y. Chen, and X. Wang. “Spintronic memristor: Compact model and statistical analysis.” Journal of Low Power Electronics 7, no. 2 (April 1, 2011): 234–44. https://doi.org/10.1166/jolpe.2011.1131.
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    • Zhu, W., H. Li, Y. Chen, and X. Wang. “Current switching in MgO-based magnetic tunneling junctions.” Ieee Transactions on Magnetics 47, no. 1 PART 2 (January 1, 2011): 156–60. https://doi.org/10.1109/TMAG.2010.2085441.
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    • Chen, Y., X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. “Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (December 1, 2010): 1724–34. https://doi.org/10.1109/TVLSI.2009.2032192.
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    • Chen, Y., W. Tian, H. Li, X. Wang, and W. Zhu. “PCMO device with high switching stability.” Ieee Electron Device Letters 31, no. 8 (August 1, 2010): 866–68. https://doi.org/10.1109/LED.2010.2050457.
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    • Chen, Y., and H. Li. “Patents relevant to cross-point memory array.” Recent Patents on Electrical Engineering 3, no. 2 (June 25, 2010): 114–24. https://doi.org/10.2174/1874476111003020114.
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    • Xi, H., J. Stricklin, H. Li, Y. Chen, X. Wang, Y. Zheng, Z. Gao, and M. X. Tang. “Spin transfer torque memory with thermal assist mechanism: A case study.” Ieee Transactions on Magnetics 46, no. 3 PART 2 (March 1, 2010): 860–65. https://doi.org/10.1109/TMAG.2009.2033674.
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    • Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.
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    • Wang, X., Y. Chen, Y. Gu, and H. Li. “Spintronic memristor temperature sensor.” Ieee Electron Device Letters 31, no. 1 (January 1, 2010): 20–22. https://doi.org/10.1109/LED.2009.2035643.
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    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.
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    • Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.
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    • Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” Ieee Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.
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    • Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” Ieee Transactions on Magnetics 44, no. 11 PART 2 (November 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.
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    • Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.
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    • Li, H., S. Bhunia, Y. Chen, K. Roy, and T. N. Vijaykumar. “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (March 1, 2004): 245–54. https://doi.org/10.1109/TVLSI.2004.824307.
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    • Agarwal, A., H. Li, and K. Roy. “A single-Vt low-leakage gated-ground cache for deep submicron.” Ieee Journal of Solid State Circuits 38, no. 2 (February 1, 2003): 319–28. https://doi.org/10.1109/JSSC.2002.807414.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, M. Albrecht, A. Amoroso, F. F. An, Q. An, et al. “Measurement of e+e−→π0π0ψ(3686) at s from 4.009 to 4.600 GeV and observation of a neutral charmoniumlike structure.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.052001.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, O. Albayrak, M. Albrecht, M. Alekseev, D. J. Ambrose, et al. “Study of η(1475) and X(1835) in radiative J/ψ decays to γϕ.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.051101.
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  • Book Sections

    • Li, Z., C. Liu, H. Li, and Y. Chen. “Neuromorphic hardware acceleration enabled by emerging technologies.” In Emerging Technology and Architecture for Big-Data Analytics, 217–44, 2017. https://doi.org/10.1007/978-3-319-54840-1_10.
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    • Chen, Y. C., Y. Wang, W. Zhang, Y. Chen, and H. H. Li. “In-place logic obfuscation for emerging nonvolatile FPGAs.” In Fundamentals of IP and SoC Security: Design, Verification, and Debug, 277–93, 2017. https://doi.org/10.1007/978-3-319-50057-7_11.
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    • Yang, C., H. Li, and Y. Chen. “Nanoscale memory architectures for neuromorphic computing.” In Security Opportunities in Nano Devices and Emerging Technologies, 215–34, 2017. https://doi.org/10.1201/9781315265056.
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    • Zhang, Y., W. Wen, H. Li, and Y. Chen. “The prospect of STT-RAM scaling.” In Metallic Spintronic Devices, 71–103, 2017. https://doi.org/10.1201/b17238.
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    • Li, H. H., M. Hu, and B. Liu. “Memristor modeling - static, statistical, and stochastic methodologies.” In Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, 313–35, 2016. https://doi.org/10.1049/PBCS029E_ch11.
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    • Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.
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    • Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.
       Full Text
    • Chen, Y., H. Li, Y. Xie, and D. Niu. “Low Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing. CRC Press, 2012.
    • Li, H. H., M. Hu, and R. E. Pino. “Statistical memristor model and its applications in neuromorphic computing.” In Advances in Neuromorphic Memristor Science and Applications, 107–31, 2012. https://doi.org/10.1007/978-94-007-4491-2_8.
       Full Text
    • Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.

  • Conference Papers

    • Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.” In Proceedings  2020 Ieee International Conference on Artificial Intelligence Circuits and Systems, Aicas 2020, 11–15, 2020. https://doi.org/10.1109/AICAS48895.2020.9073995.
       Full Text
    • Wang, Y., F. Chen, L. Song, C. J. Richard Shi, H. H. Li, and Y. Chen. “ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1472–77, 2020. https://doi.org/10.23919/DATE48585.2020.9116422.
       Full Text
    • Zhang, S., B. Li, H. H. Li, and U. Schlichtmann. “A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1426–31, 2020. https://doi.org/10.23919/DATE48585.2020.9116323.
       Full Text
    • Chen, F., W. Wen, L. Song, J. Zhang, H. H. Li, and Y. Chen. “How to obtain and run light and efficient deep learning networks.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2019-November, 2019. https://doi.org/10.1109/ICCAD45719.2019.8942106.
       Full Text
    • Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.” In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, Date 2019, 1751–56, 2019. https://doi.org/10.23919/DATE.2019.8714954.
       Full Text
    • Nixon, K. W., J. Mao, J. Shen, H. Yang, H. H. Li, and Y. Chen. “SPN dash: Fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2018. https://doi.org/10.1145/3240765.3240851.
       Full Text
    • Li, H. H., Y. Wang, and W. Wen. “Message from the technical program chairs.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:xiii–xiv, 2018. https://doi.org/10.1109/ISVLSI.2018.00006.
       Full Text
    • Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, Y. Chen, and H. Li. “MAT: A multi-strength adversarial training method to mitigate adversarial attacks.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:476–81, 2018. https://doi.org/10.1109/ISVLSI.2018.00092.
       Full Text
    • Jiang, H., K. Yamada, Z. Ren, T. Kwok, F. Luo, Q. Yang, X. Zhang, et al. “Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351276.
       Full Text
    • Li, B., F. Chen, W. Kang, W. Zhao, Y. Chen, and H. Li. “Design and Data Management for Magnetic Racetrack Memory.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351681.
       Full Text
    • Yang, Q., H. Li, and Q. Wu. “A Quantized Training Method to Enhance Accuracy of ReRAM-based Neuromorphic Systems.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351327.
       Full Text
    • Ji, H., L. Song, L. Jiang, H. H. Li, and Y. Chen. “Recom: An efficient resistive accelerator for compressed deep neural networks.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:237–40, 2018. https://doi.org/10.23919/DATE.2018.8342009.
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    • Li, B., L. Song, F. Chen, X. Qian, Y. Chen, and H. Li. “ReRAM-based accelerator for deep learning.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:815–20, 2018. https://doi.org/10.23919/DATE.2018.8342118.
       Full Text
    • Yan, B., F. Chen, Y. Zhang, C. Song, H. Li, and Y. Chen. “Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:109–12, 2018. https://doi.org/10.23919/DATE.2018.8341988.
       Full Text
    • Song, L., Y. Zhuo, X. Qian, H. Li, and Y. Chen. “GraphR: Accelerating Graph Processing Using ReRAM.” In Proceedings  International Symposium on High Performance Computer Architecture, 2018-February:531–43, 2018. https://doi.org/10.1109/HPCA.2018.00052.
       Full Text
    • Wang, P., S. Li, G. Sun, X. Wang, Y. Chen, H. Li, J. Cong, N. Xiao, and T. Zhang. “RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.” In Proceedings  International Symposium on High Performance Computer Architecture, 2018-February:518–30, 2018. https://doi.org/10.1109/HPCA.2018.00051.
       Full Text
    • Chen, F., Z. Li, W. Kang, W. Zhao, H. Li, and Y. Chen. “Process variation aware data management for magnetic skyrmions racetrack memory.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:221–26, 2018. https://doi.org/10.1109/ASPDAC.2018.8297309.
       Full Text
    • Eken, E., I. Bayram, H. H. Li, and Y. Chen. “Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:375–80, 2018. https://doi.org/10.1109/ASPDAC.2018.8297352.
       Full Text
    • Jia, X., J. Yang, Z. Wang, Y. Chen, H. H. Li, and W. Zhao. “Spintronics based stochastic computing for efficient Bayesian inference system.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:580–85, 2018. https://doi.org/10.1109/ASPDAC.2018.8297385.
       Full Text
    • Li, B., W. Wen, J. Mao, S. Li, Y. Chen, and H. H. Li. “Running sparse and low-precision neural network: When algorithm meets hardware.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:534–39, 2018. https://doi.org/10.1109/ASPDAC.2018.8297378.
       Full Text
    • Liu, X., W. Wen, X. Qian, H. Li, and Y. Chen. “Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:141–46, 2018. https://doi.org/10.1109/ASPDAC.2018.8297296.
       Full Text
    • Yan, B., C. Liu, X. Liu, Y. Chen, and H. Li. “Understanding the trade-offs of device, circuit and application in ReRAM-based neuromorphic computing systems.” In Technical Digest  International Electron Devices Meeting, Iedm, 11.4.1-11.4.4, 2018. https://doi.org/10.1109/IEDM.2017.8268371.
       Full Text
    • Liu, C., F. Liu, and H. Li. “Beyond CMOS: Memristor and its application for next generation storage and computing.” In Ecs Transactions, 85:115–25, 2018. https://doi.org/10.1149/08506.0115ecst.
       Full Text
    • Wen, W., C. Xu, C. Wu, Y. Wang, Y. Chen, and H. Li. “Coordinating Filters for Faster Deep Neural Networks.” In Proceedings of the Ieee International Conference on Computer Vision, 2017-October:658–66, 2017. https://doi.org/10.1109/ICCV.2017.78.
       Full Text
    • Broyde, L, Nixon, K, Chen, X, Li, H, and Chen, Y. "MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices." December 18, 2017.  Full Text
    • Mao, J., Z. Qin, Z. Xu, K. W. Nixon, X. Chen, H. Li, and Y. Chen. “AdaLearner: An adaptive distributed mobile learning system for neural networks.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:291–96, 2017. https://doi.org/10.1109/ICCAD.2017.8203791.
       Full Text
    • Mao, J., Z. Yang, W. Wen, C. Wu, L. Song, K. W. Nixon, X. Chen, H. Li, and Y. Chen. “MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:751–56, 2017. https://doi.org/10.1109/ICCAD.2017.8203852.
       Full Text
    • Yan, B., J. Yang, Q. Wu, Y. Chen, and H. Li. “A closed-loop design to enhance weight stability of memristor based neural network chips.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:541–48, 2017. https://doi.org/10.1109/ICCAD.2017.8203824.
       Full Text
    • Wu, C., W. Wen, T. Afzal, Y. Zhang, Y. Chen, and H. H. Li. “A compact DNN: Approaching GoogLeNet-level accuracy of classification and domain adaptation.” In Proceedings  30th Ieee Conference on Computer Vision and Pattern Recognition, Cvpr 2017, 2017-January:761–70, 2017. https://doi.org/10.1109/CVPR.2017.88.
       Full Text
    • Song, C., B. Liu, W. Wen, H. Li, and Y. Chen. “A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.” In Nvmsa 2017  6th Ieee Non Volatile Memory Systems and Applications Symposium, 2017. https://doi.org/10.1109/NVMSA.2017.8064465.
       Full Text
    • Liu, C., F. Liu, and H. Li. “Brain-inspired computing accelerated by memristor technology.” In Proceedings of the 4th Acm International Conference on Nanoscale Computing and Communication, Nanocom 2017, 2017. https://doi.org/10.1145/3109453.3123960.
       Full Text
    • Hassan, A. M., H. H. Li, and Y. Chen. “Hardware implementation of echo state networks using memristor double crossbar arrays.” In Proceedings of the International Joint Conference on Neural Networks, 2017-May:2171–77, 2017. https://doi.org/10.1109/IJCNN.2017.7966118.
       Full Text
    • Li, S., W. Wen, Y. Wang, S. Han, Y. Chen, and H. H. Li. “An FPGA design framework for CNN sparsification and acceleration.” In Proceedings  Ieee 25th Annual International Symposium on Field Programmable Custom Computing Machines, Fccm 2017, 2017. https://doi.org/10.1109/FCCM.2017.21.
       Full Text
    • Niu, D., R. Xue, T. Cai, H. Li, K. Effah, and H. Zhang. “The new large-scale RNNLM system based on distributed neuron.” In Proceedings  2017 Ieee 31st International Parallel and Distributed Processing Symposium Workshops, Ipdpsw 2017, 433–36, 2017. https://doi.org/10.1109/IPDPSW.2017.21.
       Full Text
    • Liu, C., M. Hu, J. P. Strachan, and H. H. Li. “Rescuing Memristor-based Neuromorphic Design with High Defects.” In Proceedings  Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062310.
       Full Text
    • Wang, Y., W. Wen, B. Liu, D. Chiarulli, and H. H. Li. “Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks.” In Proceedings  Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062256.
       Full Text
    • Cheng, H. P., W. Wen, C. Wu, S. Li, H. Li, and Y. Chen. “Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.” In Proceedings of the 2017 Design, Automation and Test in Europe, Date 2017, 139–44, 2017. https://doi.org/10.23919/DATE.2017.7926972.
       Full Text
    • Hassan, A. M., C. Yang, C. Liu, H. Li, and Y. Chen. “Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.” In Proceedings of the 2017 Design, Automation and Test in Europe, Date 2017, 776–81, 2017. https://doi.org/10.23919/DATE.2017.7927094.
       Full Text
    • Song, L., X. Qian, H. Li, and Y. Chen. “PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.” In Proceedings  International Symposium on High Performance Computer Architecture, 541–52, 2017. https://doi.org/10.1109/HPCA.2017.55.
       Full Text
    • Cline, B. T., S. Heinrich-Barna, P. J. Wright, H. Li, V. Viswanath, S. Hu, P. Wesling, G. Qu, S. Ghosh, and A. A. Iranmanesh. “Welcome.” In Proceedings  International Symposium on Quality Electronic Design, Isqed, 2017. https://doi.org/10.1109/ISQED.2017.7918277.
       Full Text
    • Liu, C., Q. Yang, C. Zhang, H. Jiang, Q. Wu, and H. Li. “A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 647–52, 2017. https://doi.org/10.1109/ASPDAC.2017.7858397.
       Full Text
    • Min, C., J. Guo, H. Li, and Y. Chen. “Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 764–69, 2017. https://doi.org/10.1109/ASPDAC.2017.7858416.
       Full Text
    • Wang, Y., W. Wen, L. Song, and H. Li. “Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 776–81, 2017. https://doi.org/10.1109/ASPDAC.2017.7858418.
       Full Text
    • Li, H. H., P. Ghosal, and T. Theocharides. “Message from the Technical Program Chairs.” In Proceedings  2016 Ieee International Symposium on Nanoelectronic and Information Systems, Inis 2016, xiii–xiv, 2017. https://doi.org/10.1109/iNIS.2016.007.
       Full Text
    • Li, Hai. “Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies.” In 2017 International Symposium on Vlsi Design, Automation and Test (Vlsi Dat). IEEE, 2017.
       Link to Item
    • Wen, W., C. Xu, F. Yan, C. Wu, Y. Wang, Y. Chen, and H. Li. “TernGrad: Ternary gradients to reduce communication in distributed deep learning.” In Advances in Neural Information Processing Systems, 2017-December:1510–20, 2017.
    • Yan, B., Z. Li, Y. Chen, and H. Li. “RAM and TCAM designs by using STT-MRAM.” In 2016 16th Non Volatile Memory Technology Symposium, Nvmts 2016, 18–22, 2016. https://doi.org/10.1109/NVMTS.2016.7781514.
       Full Text
    • Song, C., B. Liu, C. Liu, H. Li, and Y. Chen. “Design techniques of eNVM-enabled neuromorphic computing systems.” In Proceedings of the 34th Ieee International Conference on Computer Design, Iccd 2016, 674–77, 2016. https://doi.org/10.1109/ICCD.2016.7753356.
       Full Text
    • Liu, C., Y. Chen, and H. Li. “Neural processor design enabled by memristor technology.” In 2016 Ieee International Conference on Rebooting Computing, Icrc 2016  Conference Proceedings, 2016. https://doi.org/10.1109/ICRC.2016.7738693.
       Full Text
    • Li, S., Y. Wang, W. Wen, Y. Chen, and H. Li. “A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 07-10-November-2016, 2016. https://doi.org/10.1145/2966986.2966987.
       Full Text
    • Yang, C., B. Liu, H. Li, Y. Chen, W. Wen, M. Barnell, Q. Wu, and J. Rajendran. “Security of neuromorphic computing: Thwarting learning attacks using memristor's obsolescence effect.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 07-10-November-2016, 2016. https://doi.org/10.1145/2966986.2967074.
       Full Text
    • Yang, C., C. Wu, H. Li, Y. Chen, M. Barnell, and Q. Wu. “Security challenges in smart surveillance systems and the solutions based on emerging nano-devices.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 07-10-November-2016, 2016. https://doi.org/10.1145/2966986.2980092.
       Full Text
    • Wu, C., H. P. Cheng, S. Li, H. H. Li, and Y. Chen. “ApesNet: A pixel-wise efficient segmentation network.” In Proceedings of the 14th Acm/Ieee Symposium on Embedded Systems for Real Time Multimedia, Estimedia 2016, 2–8, 2016. https://doi.org/10.1145/2993452.2994306.
       Full Text
    • Cheng, H. P., W. Wen, C. Song, B. Liu, H. Li, and Y. Chen. “Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.” In Proceedings of the 2016 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2016, 185–90, 2016. https://doi.org/10.1145/2950067.2950096.
       Full Text
    • Li, H. H., and X. Li. “Message from the general chairs.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, Vol. 2016-September, 2016. https://doi.org/10.1109/ISVLSI.2016.4.
       Full Text
    • Liu, C., Q. Yang, B. Yan, J. Yang, X. Du, W. Zhu, H. Jiang, Q. Wu, M. Barnell, and H. H. Li. “A memristor crossbar based computing engine optimized for high speed and accuracy.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2016-September:110–15, 2016. https://doi.org/10.1109/ISVLSI.2016.46.
       Full Text
    • Guo, J., C. Min, T. Cai, H. Li, and Y. Chen. “ObjNandSim: Object-based NAND flash device simulator.” In 2016 5th Non Volatile Memory Systems and Applications Symposium, Nvmsa 2016, 2016. https://doi.org/10.1109/NVMSA.2016.7547179.
       Full Text
    • Li, Z., X. Bi, H. H. Li, Y. Chen, J. Qin, P. Guo, W. Kong, et al. “Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.” In Proceedings of the International Symposium on Low Power Electronics and Design, 4–9, 2016. https://doi.org/10.1145/2934583.2934611.
       Full Text
    • Chakraborty, S., S. Joshi, Q. Xia, H. Li, Y. Chen, H. Jiang, Q. Wu, M. Barnell, and J. J. Yang. “Built-in selectors self-assembled into memristors.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2016-July:181–84, 2016. https://doi.org/10.1109/ISCAS.2016.7527200.
       Full Text
    • Li, S., X. Liu, M. Mao, H. H. Li, Y. Chen, B. Li, and Y. Wang. “Heterogeneous systems with reconfigurable neuromorphic computing accelerators.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2016-July:125–28, 2016. https://doi.org/10.1109/ISCAS.2016.7527186.
       Full Text
    • Liu, B., C. Yang, H. Li, Y. Chen, Q. Wu, and M. Barnell. “Security of neuromorphic systems: Challenges and solutions.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2016-July:1326–29, 2016. https://doi.org/10.1109/ISCAS.2016.7527493.
       Full Text
    • Yan, B., A. M. Mahmoud, J. J. Yang, Q. Wu, Y. Chen, and H. H. Li. “A neuromorphic ASIC design using one-selector-one-memristor crossbar.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2016-July:1390–93, 2016. https://doi.org/10.1109/ISCAS.2016.7527509.
       Full Text
    • Mao, M., W. Wen, X. Liu, J. Hu, D. Wang, Y. Chen, and H. Li. “TEMP: Thread batch enabled memory partitioning for GPU.” In Proceedings  Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2898103.
       Full Text
    • Wen, W., C. Wu, Y. Wang, K. Nixon, Q. Wu, M. Barnell, H. Li, and Y. Chen. “A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.” In Proceedings  Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2897968.
       Full Text
    • Eken, E., I. Bayram, Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. “Spin-hall assisted STT-RAM design and discussion.” In Proceedings of the 18th Acm/Ieee System Level Interconnect Prediction 2016 Workshop, Slip 2016, 2016. https://doi.org/10.1145/2947357.2947360.
       Full Text
    • Cline, B., H. H. Li, G. Qu, S. Mukhopadhyay, V. Viswanath, A. A. Iranmanesh, P. J. Wright, and P. Wesling. “WELCOME to ISQED 2016.” In Proceedings  International Symposium on Quality Electronic Design, Isqed, Vol. 2016-May, 2016. https://doi.org/10.1109/ISQED.2016.7479143.
       Full Text
    • Yang, C., B. Liu, Y. Wang, Y. Chen, H. Li, X. Zhang, and G. Sun. “The applications of NVM technology in hardware security.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 18-20-May-2016:311–16, 2016. https://doi.org/10.1145/2902961.2903043.
       Full Text
    • Wang, X., M. Mao, E. Eken, W. Wen, H. Li, and Y. Chen. “Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.” In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016, 762–67, 2016. https://doi.org/10.3850/9783981537079_0419.
       Full Text
    • Wen, W., M. Mao, H. Li, Y. Chen, Y. Pei, and N. Ge. “A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.” In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016, 1285–90, 2016. https://doi.org/10.3850/9783981537079_0917.
       Full Text
    • Liu, B., X. Liu, C. Liu, W. Wen, M. Meng, H. Li, and Y. Chen. “Hardware acceleration for neuromorphic computing: An evolving view.” In 2015 15th Non Volatile Memory Technology Symposium, Nvmts 2015, 2016. https://doi.org/10.1109/NVMTS.2015.7457496.
       Full Text
    • Zhang, X., S. Guangyu, Y. Zhang, Y. Chen, H. Li, W. Wen, and J. Di. “A novel PUF based on cell error rate distribution of STT-RAM.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 25-28-January-2016:342–47, 2016. https://doi.org/10.1109/ASPDAC.2016.7428035.
       Full Text
    • Li, H., X. Bi, and Z. Sun. “The evolutionary spintronic technologies and their usage in high performance computing.” In International System on Chip Conference, 2016-February:350–55, 2016. https://doi.org/10.1109/SOCC.2015.7406981.
       Full Text
    • Cline, Brian, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, and Ali Iranmanesh. “Welcome.” In Isqed. IEEE, 2016.
    • Guo, Jing, Chao Liu, and Philippe Poignet. “Effect of Non-passive Operator on Enhanced Wave-Based Teleoperator for Robotic-Assisted Surgery: First Case Study,” 1–14. Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-30674-2_1.
       Full Text
    • Li, Hong-qi, Qing-wei Liu, Jue-shu Fang, and Yu-long Wang. “Synthesis and Characterization of 3-butyryloxy-16-(beta-naphthylmethylene)-5 alpha-androstane-17-one.” In Proceedings of the 2016 International Conference on Biomedical and Biological Engineering, 97–101, 2016.
       Link to Item
    • Wen, W., C. Wu, Y. Wang, Y. Chen, and H. Li. “Learning structured sparsity in deep neural networks.” In Advances in Neural Information Processing Systems, 2082–90, 2016.
    • Liang, H., Y. C. Chen, T. Luo, W. Zhang, H. Li, and B. He. “Hierarchical Library Based Power Estimator for Versatile FPGAs.” In Proceedings  Ieee 9th International Symposium on Embedded Multicore/Manycore Socs, Mcsoc 2015, 25–32, 2015. https://doi.org/10.1109/MCSoC.2015.44.
       Full Text
    • Li, Z., C. Liu, Y. Wang, B. Yan, C. Yang, J. Yang, and H. Li. “An overview on memristor crossabr based neuromorphic circuit and architecture.” In Ieee/Ifip International Conference on Vlsi and System on Chip, Vlsi Soc, 2015-October:52–56, 2015. https://doi.org/10.1109/VLSI-SoC.2015.7314391.
       Full Text
    • Liang, H., W. Zhang, S. Sinha, Y. C. Chen, and H. Li. “Hierarchical library based power estimator for versatile FPGAs.” In 25th International Conference on Field Programmable Logic and Applications, Fpl 2015, 2015. https://doi.org/10.1109/FPL.2015.7293969.
       Full Text
    • Li, H. H., C. Liu, B. Yan, C. Yang, L. Song, Z. Li, Y. Chen, W. Zhu, Q. Wu, and H. Jiang. “Spiking-based matrix computation by leveraging memristor crossbar array.” In 2015 Ieee Symposium on Computational Intelligence for Security and Defense Applications, Cisda 2015  Proceedings, 43–46, 2015. https://doi.org/10.1109/CISDA.2015.7208626.
       Full Text
    • Wang, Y., T. Tang, L. Xia, B. Li, P. Gu, H. Li, Y. Xie, and H. Yang. “Energy efficient RRAM spiking neural network for real time classification.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 20-22-May-2015:189–94, 2015. https://doi.org/10.1145/2742060.2743756.
       Full Text
    • Wang, Y., W. Wen, M. Hu, and H. Li. “A novel true random number generator design leveraging emerging memristor technology.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 20-22-May-2015:271–76, 2015. https://doi.org/10.1145/2742060.2742088.
       Full Text
    • Yan, B., Z. Li, Y. Zhang, J. Yang, W. Zhao, P. C. F. Chia, and H. Li. “A high-speed robust NVM-TCAM design using body bias feedback.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 20-22-May-2015:69–74, 2015. https://doi.org/10.1145/2742060.2742077.
       Full Text
    • Zhang, Y., B. Yan, W. Wu, H. Li, and Y. Chen. “Giant spin hall effect (GSHE) logic design for low power application.” In Proceedings  Design, Automation and Test in Europe, Date, 2015-April:1000–1005, 2015. https://doi.org/10.7873/date.2015.1118.
       Full Text
    • Li, H., X. Liu, M. Mao, Y. Chen, Q. Wu, and M. Barnell. “Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).” In Proceedings of the 14th International Symposium on Integrated Circuits, Isic 2014, 124–27, 2015. https://doi.org/10.1109/ISICIR.2014.7029530.
       Full Text
    • Tang, T., R. Luo, B. Li, H. Li, Y. Wang, and H. Yang. “Energy efficient spiking neural network design with RRAM devices.” In Proceedings of the 14th International Symposium on Integrated Circuits, Isic 2014, 268–71, 2015. https://doi.org/10.1109/ISICIR.2014.7029565.
       Full Text
    • Liu, B., H. Li, Y. Chen, X. Li, T. Huang, Q. Wu, and M. Barnell. “Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2015-January:63–70, 2015. https://doi.org/10.1109/ICCAD.2014.7001330.
       Full Text
    • Eken, E., Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. “Spin-hall assisted STT-RAM design and discussion.” In 2015 Ieee International Magnetics Conference, Intermag 2015, 2015. https://doi.org/10.1109/INTMAG.2015.7156644.
       Full Text
    • Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel: A novel NAND flash storage system design for LDPC latency reduction.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744843.
       Full Text
    • Li, H., B. Liu, X. Liu, M. Mao, Y. Chen, Q. Wu, and Q. Qiu. “The applications of memristor devices in next-generation cortical processor designs.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2015-July:17–20, 2015. https://doi.org/10.1109/ISCAS.2015.7168559.
       Full Text
    • Li, S., C. Wu, H. Li, B. Li, Y. Wang, and Q. Qiu. “FPGA acceleration of recurrent neural network based language model.” In Proceedings  2015 Ieee 23rd Annual International Symposium on Field Programmable Custom Computing Machines, Fccm 2015, 111–18, 2015. https://doi.org/10.1109/FCCM.2015.50.
       Full Text
    • Li, Z., B. Yan, L. Yang, W. Zhao, Y. Chen, and H. Li. “A new self-reference sensing scheme for TLC MRAM.” In Proceedings  Ieee International Symposium on Circuits and Systems, 2015-July:593–96, 2015. https://doi.org/10.1109/ISCAS.2015.7168703.
       Full Text
    • Liu, B., C. Wu, H. Li, Y. Chen, Q. Wu, M. Barnell, and Q. Qiu. “Cloning your mind: Security challenges in cognitive system designs and their solutions.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2747915.
       Full Text
    • Liu, B., H. Li, Y. Chen, X. Li, Q. Wu, and T. Huang. “Vortex: Variation-aware training for memristor X-bar.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744930.
       Full Text
    • Liu, C., B. Yan, C. Yang, L. Song, Z. Li, B. Liu, Y. Chen, H. Li, Q. Wu, and H. Jiang. “A spiking neuromorphic design with resistive crossbar.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744783.
       Full Text
    • Liu, X., M. Mao, B. Liu, H. Li, Y. Chen, B. Li, Y. Wang, et al. “RENO: A high-efficient reconfigurable neuromorphic computing accelerator design.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744900.
       Full Text
    • Liu, X., M. Mao, X. Bi, H. Li, and Y. Chen. “An efficient STT-RAM-based register file in GPU architectures.” In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 490–95, 2015. https://doi.org/10.1109/ASPDAC.2015.7059054.
       Full Text
    • Mao, M., J. Hu, Y. Chen, and H. Li. “VWS: A versatile warp scheduler for exploring diverse cache localities of GPGPU applications.” In Proceedings  Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744931.
       Full Text
    • Wang, Yu-ying, Long-biao He, Hai-jiang Zhu, and Ping Yang. “CONSISTENCY OF SURFACE PULSE AND RECIPROCITY CALIBRATION OF PIEZOELECTRIC AE SENSORS.” In Proceedings of the 2015 Symposium on Piezoelectricity, Acoustic Waves and Device Applications, edited by X. Tao, X. Zhao, C. Wang, and F. Yu, 189–92. IEEE, 2015.
       Link to Item
    • Wright, P. J., A. Raychowdhury, B. Liu, S. Mukhopadhyay, H. H. Li, A. A. Iranmanesh, S. M. Alam, and P. Wesling. “Welcome to ISQED 2015.” In Proceedings  International Symposium on Quality Electronic Design, Isqed, Vol. 2015-April, 2015. https://doi.org/10.1109/ISQED.2015.7085359.
       Full Text
    • Zhang, C., G. Sun, W. Zhang, F. Mi, H. Li, and W. Zhao. “Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.” In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 100–105, 2015. https://doi.org/10.1109/ASPDAC.2015.7058988.
       Full Text
    • Chen, L., C. Li, T. Huang, X. He, H. Li, and Y. Chen. “STDP learning rule based on memristor with STDP property.” In Proceedings of the International Joint Conference on Neural Networks, 1–6, 2014. https://doi.org/10.1109/IJCNN.2014.6889506.
       Full Text
    • Hu, M., Y. Wang, Q. Qiu, Y. Chen, and H. Li. “The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 831–36, 2014. https://doi.org/10.1109/ASPDAC.2014.6742993.
       Full Text
    • Wang, J., Y. Tim, W. F. Wong, Z. L. Ong, Z. Sun, and H. H. Li. “A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 610–15, 2014. https://doi.org/10.1109/ASPDAC.2014.6742958.
       Full Text
    • Liu, X., M. Mao, H. Li, Y. Chen, H. Jiang, J. J. Yang, Q. Wu, and M. Barnell. “A heterogeneous computing system with memristor-based neuromorphic accelerators.” In 2014 Ieee High Performance Extreme Computing Conference, Hpec 2014, 2014. https://doi.org/10.1109/HPEC.2014.7040986.
       Full Text
    • Cavallaro, J. R., T. Zhang, A. K. Jones, and H. Li. “GLSVLSI'14 chairs' welcome.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 2014.
    • Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A new field-assisted access scheme of STT-RAM with self-reference capability.” In Proceedings  Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2593075.
       Full Text
    • Hu, X., G. Feng, H. Li, Y. Chen, and S. Duan. “An adjustable memristor model and its application in small-world neural networks.” In Proceedings of the International Joint Conference on Neural Networks, 7–14, 2014. https://doi.org/10.1109/IJCNN.2014.6889605.
       Full Text
    • Li, B., Y. Wang, Y. Chen, H. H. Li, and H. Yang. “ICE: Inline calibration for memristor crossbar-based computing engine.” In Proceedings  Design, Automation and Test in Europe, Date, 2014. https://doi.org/10.7873/DATE2014.197.
       Full Text
    • Li, H., M. Hu, C. Li, and S. Duan. “Memristor modeling - Static, statistical, and stochastic methodologies.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 406–11, 2014. https://doi.org/10.1109/ISVLSI.2014.108.
       Full Text
    • Li, H., M. Hu, X. Liu, M. Mao, C. Li, and S. Duan. “Emerging memristor technology enabled next generation cortical processor.” In International System on Chip Conference, 377–82, 2014. https://doi.org/10.1109/SOCC.2014.6948958.
       Full Text
    • Liu, C., and H. Li. “A weighted sensing scheme for ReRAM-based cross-point memory array.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 65–70, 2014. https://doi.org/10.1109/ISVLSI.2014.32.
       Full Text
    • Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “Exploration of GPGPU register file architecture using domain-wall-shift- write based racetrack memory.” In Proceedings  Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2593137.
       Full Text
    • Park, E., S. Yoo, S. Lee, and H. Li. “Accelerating graph computation with racetrack memory and pointer-assisted graph representation.” In Proceedings  Design, Automation and Test in Europe, Date, 2014. https://doi.org/10.7873/DATE2014.172.
       Full Text
    • Qiu, Q., Z. Li, K. Ahmed, H. H. Li, and M. Hu. “Neuromorphic acceleration for context aware text image recognition.” In Ieee Workshop on Signal Processing Systems, Sips: Design and Implementation, 2014. https://doi.org/10.1109/SiPS.2014.6986098.
       Full Text
    • Sun, Z., X. Bi, A. K. Jones, and H. Li. “Design exploration of racetrack lower-level caches.” In Proceedings of the International Symposium on Low Power Electronics and Design, 263–66, 2014. https://doi.org/10.1145/2627369.2627651.
       Full Text
    • Wang, J., P. Roy, W. F. Wong, X. Bi, and H. Li. “Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.” In 2014 32nd Ieee International Conference on Computer Design, Iccd 2014, 133–38, 2014. https://doi.org/10.1109/ICCD.2014.6974672.
       Full Text
    • Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32nd Ieee International Conference on Computer Design (Iccd), 126–31. IEEE, 2014.
       Link to Item
    • Wu, Q., B. Liu, Y. Chen, H. Li, Q. Chen, and Q. Qiu. “Bio-inspired computing with resistive memories - Models, architectures and applications.” In Proceedings  Ieee International Symposium on Circuits and Systems, 834–37, 2014. https://doi.org/10.1109/ISCAS.2014.6865265.
       Full Text
    • Wang, J., Y. Tim, W. F. Wong, and H. H. Li. “A practical low-power memristor-based analog neural branch predictor.” In Proceedings of the International Symposium on Low Power Electronics and Design, 175–80, 2013. https://doi.org/10.1109/ISLPED.2013.6629290.
       Full Text
    • Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.
       Full Text
    • Chen, Q., Q. Qiu, H. Li, and Q. Wu. “A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 202–5, 2013. https://doi.org/10.1109/ICCAD.2013.6691119.
       Full Text
    • Ji, F., H. H. Li, B. Wysocki, C. Thiem, and N. McDonald. “Memristor-based synapse design and a case study in reconfigurable systems.” In Proceedings of the International Joint Conference on Neural Networks, 2013. https://doi.org/10.1109/IJCNN.2013.6706776.
       Full Text
    • Zhang, Y., I. Bayram, Y. Wang, H. Li, and Y. Chen. “ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 9–16, 2013. https://doi.org/10.1109/ICCAD.2013.6691091.
       Full Text
    • Chen, Z., L. Zhang, X. Bi, and H. Li. “A pseudo-weighted sensing scheme for memristor based cross-point memory.” In Proceedings of the 2013 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2013, 38–39, 2013. https://doi.org/10.1109/NanoArch.2013.6623039.
       Full Text
    • Hu, M., H. Li, Y. Chen, Q. Wu, and G. S. Rose. “BSB training scheme implementation on memristor-based circuit.” In Proceedings of the 2013 Ieee Symposium on Computational Intelligence for Security and Defense Applications, Cisda 2013  2013 Ieee Symposium Series on Computational Intelligence, Ssci 2013, 80–87, 2013. https://doi.org/10.1109/CISDA.2013.6595431.
       Full Text
    • Sun, Z., W. Wu, and H. Li. “Cross-layer racetrack memory design for ultra high density and low power consumption.” In Proceedings  Design Automation Conference, 2013. https://doi.org/10.1145/2463209.2488799.
       Full Text
    • Mao, M., H. Li, A. K. Jones, and Y. Chen. “Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 55–60, 2013. https://doi.org/10.1145/2483028.2483060.
       Full Text
    • Bi, X., M. A. Weldon, and H. Li. “STT-RAM designs supporting dual-port accesses.” In Proceedings  Design, Automation and Test in Europe, Date, 853–58, 2013. https://doi.org/10.7873/date.2013.180.
       Full Text
    • Chen, Y. C., W. Zhang, and H. H. Li. “A hardware security scheme for RRAM-based FPGA.” In 2013 23rd International Conference on Field Programmable Logic and Applications, Fpl 2013  Proceedings, 2013. https://doi.org/10.1109/FPL.2013.6645556.
       Full Text
    • Guo, J., W. Wen, Y. Z. Li, S. Li, H. Li, and Y. Chen. “DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems.” In Proceedings  Design, Automation and Test in Europe, Date, 380–85, 2013. https://doi.org/10.7873/date.2013.087.
       Full Text
    • Li, Hong-jun, Zheng-guang Xie, and Wei Hu. “An Image Compression Method using Sparse Representation and Grey Relation.” In Proceedings of 2013 Ieee International Conference on Grey Systems and Intelligent Services (Gsis), 53–56, 2013.
       Link to Item
    • Liu, B., M. Hu, H. Li, Z. H. Mao, Y. Chen, T. Huang, and W. Zhang. “Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.” In Proceedings  Design Automation Conference, 2013. https://doi.org/10.1145/2463209.2488741.
       Full Text
    • Chen, Y. C., W. Wang, H. Li, and W. Zhang. “Non-volatile 3D stacking RRAM-based FPGA.” In Proceedings  22nd International Conference on Field Programmable Logic and Applications, Fpl 2012, 367–72, 2012. https://doi.org/10.1109/FPL.2012.6339206.
       Full Text
    • Chen, Y. C., W. Wang, W. Zhang, and H. Li. “uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.” In Fpt 2012  2012 International Conference on Field Programmable Technology, 80–86, 2012. https://doi.org/10.1109/FPT.2012.6412116.
       Full Text
    • Bi, X., H. Li, and J. J. Kim. “Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design.” In Proceedings  2012 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2012, 374–79, 2012. https://doi.org/10.1109/ISVLSI.2012.56.
       Full Text
    • Chen, Y. C., H. Li, and W. Zhang. “A novel peripheral circuit for RRAM-based LUT.” In Iscas 2012  2012 Ieee International Symposium on Circuits and Systems, 1811–14, 2012. https://doi.org/10.1109/ISCAS.2012.6271619.
       Full Text
    • Sun, Z., H. Li, and W. Wu. “A dual-mode architecture for fast-switching STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 45–50, 2012. https://doi.org/10.1145/2333660.2333673.
       Full Text
    • Sun, Z., X. Bi, and H. Li. “Process variation aware data management for STT-RAM cache design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 179–84, 2012. https://doi.org/10.1145/2333660.2333706.
       Full Text
    • Hu, M., H. Li, Q. Wu, G. S. Rose, and Y. Chen. “Memristor crossbar based hardware realization of BSB recall function.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252563.
       Full Text
    • Wang, H., H. Li, and R. E. Pino. “Memristor-based synapse design and training scheme for neuromorphic computing architecture.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252577.
       Full Text
    • Hu, M., H. Li, Q. Wu, and G. S. Rose. “Hardware realization of BSB recall function using memristor crossbar arrays.” In Proceedings  Design Automation Conference, 498–503, 2012. https://doi.org/10.1145/2228360.2228448.
       Full Text
    • Pino, R. E., H. Li, Y. Chen, M. Hu, and B. Liu. “Statistical memristor modeling and case study in neuromorphic computing.” In Proceedings  Design Automation Conference, 585–90, 2012. https://doi.org/10.1145/2228360.2228466.
       Full Text
    • Bi, X., C. Zhang, H. Li, Y. Chen, and R. E. Pino. “Spintronic memristor based temperature sensor design with CMOS current reference.” In Proceedings  Design, Automation and Test in Europe, Date, 1301–6, 2012.
    • Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Architecting a common-source-line array for bipolar non-volatile memory devices.” In Proceedings  Design, Automation and Test in Europe, Date, 1451–54, 2012.
    • Chen, X., J. Zeng, Y. Chen, W. Zhang, and H. Li. “Fine-grained dynamic voltage scaling on OLED display.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 807–12, 2012. https://doi.org/10.1109/ASPDAC.2012.6165066.
       Full Text
    • Chen, Y. C., W. Zhang, and H. Li. “A look up table design with 3D bipolar RRAMs.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 73–78, 2012. https://doi.org/10.1109/ASPDAC.2012.6165051.
       Full Text
    • Bi, X., Z. Sun, H. Li, and W. Wu. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 88–94, 2012. https://doi.org/10.1145/2429384.2429401.
       Full Text
    • Hu, M., H. Li, and R. E. Pino. “Fast statistical model of TiO 2 thin-film memristor and design implication.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 345–52, 2011. https://doi.org/10.1109/ICCAD.2011.6105353.
       Full Text
    • Joshi, R., R. Kanj, P. Wang, and H. H. Li. “Universal statistical cure for predicting memory loss.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 236–39, 2011. https://doi.org/10.1109/ICCAD.2011.6105333.
       Full Text
    • Sun, Z., X. Bi, H. Li, W. F. Wong, Z. L. Ong, X. Zhu, and W. Wu. “Multi retention level STT-RAM cache designs with a dynamic refresh scheme.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 329–38, 2011. https://doi.org/10.1145/2155620.2155659.
       Full Text
    • Xue, C. J., Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li. “Emerging non-volatile memories: Opportunities and challenges.” In Embedded Systems Week 2011, Esweek 2011  Proceedings of the 9th Ieee/Acm/Ifip International Conference on Hardware/Software Codesign and System Synthesis, Codes+Isss’11, 325–34, 2011. https://doi.org/10.1145/2039370.2039420.
       Full Text
    • Wang, P., X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu. “A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.” In Proceedings of the Custom Integrated Circuits Conference, 2011. https://doi.org/10.1109/CICC.2011.6055392.
       Full Text
    • Chen, Y., W. F. Wong, H. Li, and C. K. Koh. “Processor caches built using multi-level spin-transfer torque RAM cells.” In Proceedings of the International Symposium on Low Power Electronics and Design, 73–78, 2011. https://doi.org/10.1109/ISLPED.2011.5993610.
       Full Text
    • Chen, Y. C., H. Li, W. Zhang, and R. E. Pino. “3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design.” In Proceedings of the 2011 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2011, 59–64, 2011. https://doi.org/10.1109/NANOARCH.2011.5941484.
       Full Text
    • Chen, Y. C., H. Li, Y. Chen, and R. E. Pino. “3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.” In Proceedings  Design, Automation and Test in Europe, Date, 583–86, 2011.
    • Chen, Y., and H. Li. “Emerging sensing techniques for emerging memories.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 204–10, 2011. https://doi.org/10.1109/ASPDAC.2011.5722185.
       Full Text
    • Joshi, Rajiv, Rouwaida Kanj, Peiyuan Wang, and Hai Helen Li. “Universal Statistical Cure For Predicting Memory Loss (Invited Paper).” In 2011 Ieee/Acm International Conference on Computer Aided Design (Iccad), 236–39. IEEE, 2011.
       Link to Item
    • Chen, Y., H. Li, X. Wang, and J. Park. “Applications of TMR devices in solid state circuits and systems.” In 2010 International Soc Design Conference, Isocc 2010, 252–55, 2010. https://doi.org/10.1109/SOCDC.2010.5682923.
       Full Text
    • Sun, Z., H. Li, Y. Chen, and X. Wang. “Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 432–37, 2010. https://doi.org/10.1109/ICCAD.2010.5653720.
       Full Text
    • Chen, Y., H. Li, and X. Wang. “Spintronic devices: From memory to memristor.” In 2010 International Conference on Communications, Circuits and Systems, Icccas 2010  Proceedings, 811–16, 2010. https://doi.org/10.1109/ICCCAS.2010.5581868.
       Full Text
    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 1–6, 2010. https://doi.org/10.1145/1840845.1840847.
       Full Text
    • Chen, Y., X. Wang, W. Zhu, H. Li, Z. Sun, G. Sun, and Y. Xie. “Access scheme of multi-level cell spin-transfer torque random access memory and its optimization.” In Midwest Symposium on Circuits and Systems, 1109–12, 2010. https://doi.org/10.1109/MWSCAS.2010.5548848.
       Full Text
    • Li, H., and Y. Chen. “Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture.” In Midwest Symposium on Circuits and Systems, 1–4, 2010. https://doi.org/10.1109/MWSCAS.2010.5548590.
       Full Text
    • Chen, Y., X. Wang, Z. Sun, and H. Li. “The application of spintronic devices in magnetic bio-sensing.” In Proceedings of the 2nd Asia Symposium on Quality Electronic Design, Asqed 2010, 230–34, 2010. https://doi.org/10.1109/ASQED.2010.5548244.
       Full Text
    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM).” In Proceedings  Design, Automation and Test in Europe, Date, 148–53, 2010.
    • Li, H., and M. Hu. “Compact model of memristors and its application in computing systems.” In Proceedings  Design, Automation and Test in Europe, Date, 673–78, 2010.
    • Chen, Y., W. Tian, H. Li, X. Wang, and W. Zhu. “Scalability of PCMO-based resistive switch device in DSM technologies.” In Proceedings of the 11th International Symposium on Quality Electronic Design, Isqed 2010, 327–32, 2010. https://doi.org/10.1109/ISQED.2010.5450447.
       Full Text
    • Sun, G., Y. Joo, Y. Chen, D. Niu, Y. Xie, and H. Li. “A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.” In Proceedings  International Symposium on High Performance Computer Architecture, 2010. https://doi.org/10.1109/hpca.2010.5416650.
       Full Text
    • Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.” In Proceedings  Ieee International Conference on Computer Design: Vlsi in Computers and Processors, 268–74, 2009. https://doi.org/10.1109/ICCD.2009.5413145.
       Full Text
    • Li, H., H. Xi, Y. Chen, J. Stricklin, X. Wang, and T. Zhang. “Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration.” In Proceedings of the 2009 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2009, 217–22, 2009. https://doi.org/10.1109/ISVLSI.2009.17.
       Full Text
    • Li, Hai, and Yiran Chen. “An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures.” In Date: 2009 Design, Automation & Test in Europe Conference & Exhibition, Vols 1 3, 731–36. IEEE, 2009.
       Link to Item
    • Dong, X., X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.” In Proceedings  Design Automation Conference, 554–59, 2008. https://doi.org/10.1109/DAC.2008.4555878.
       Full Text
    • Chen, Y., X. Wang, H. Li, H. Liu, and D. V. Dimitrov. “Design margin exploration of Spin-Torque Transfer RAM (SPRAM).” In Proceedings of the 9th International Symposium on Quality Electronic Design, Isqed 2008, 684–90, 2008. https://doi.org/10.1109/ISQED.2008.4479820.
       Full Text
    • Chen, Yiran, Xiaobin Wang, Hai Li, Harry Liu, and Dimitar V. Dimitrov. “Design margin exploration of spin-torque transfer RAM (SPRAM).” In Isqed 2008: Proceedings of the Ninth International Symposium on Quality Electronic Design, 684–90. IEEE COMPUTER SOC, 2008. https://doi.org/10.1109/ISQED.2008.140.
       Full Text  Link to Item
    • Chen, Y., H. Li, J. Li, and C. K. Koh. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” In Proceedings of the International Symposium on Low Power Electronics and Design, 195–200, 2007. https://doi.org/10.1145/1283780.1283822.
       Full Text
    • Wong, W. F., C. K. Kon, Y. Chen, and H. Li. “VOSCH: Voltage scaled cache hierarchies.” In 2007 Ieee International Conference on Computer Design, Iccd 2007, 496–503, 2007. https://doi.org/10.1109/ICCD.2007.4601944.
       Full Text
    • Li, H., Y. Chen, K. Roy, and C. K. Koh. “SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2006:158–63, 2006.
    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Cascaded carry-select adder (C² SA): A new structure for low-power CSA design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 115–18, 2005.
    • Chen, Y. R., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Cicc: Proceedings of the Ieee 2005 Custom Integrated Circuits Conference, 775–78. IEEE, 2005.
       Link to Item
    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Proceedings of the Custom Integrated Circuits Conference, 2005:775–78, 2005. https://doi.org/10.1109/CICC.2005.1568783.
       Full Text
    • Li, H., C. Y. Cher, T. N. Vijaykumar, and K. Roy. “VSV: L2-miss-driven variable supply-voltage scaling for low power.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 2003-January:19–28, 2003. https://doi.org/10.1109/MICRO.2003.1253180.
       Full Text
    • Li, H., S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy. “Deterministic clock gating for microprocessor power reduction.” In Proceedings  International Symposium on High Performance Computer Architecture, 12:113–22, 2003. https://doi.org/10.1109/HPCA.2003.1183529.
       Full Text
    • Agarwal, A., H. Li, and K. Roy. “DRG-Cache: A data retention gated-ground cache for low power.” In Proceedings  Design Automation Conference, 473–78, 2002. https://doi.org/10.1109/dac.2002.1012671.
       Full Text
    • Bhunia, S., H. Li, and K. Roy. “A high performance IDDQ testable cache for scaled CMOS technologies.” In Proceedings of the Asian Test Symposium, 2002-January:157–62, 2002. https://doi.org/10.1109/ATS.2002.1181704.
       Full Text
    • Chen, Ying, Peng Liu, and Zhi Wu Yu. “Research on the Sol-Gel Method of Preparing Ternary Nano SiO₂-Al₂O₃-TiO₂ Materials.” In Key Engineering Materials, 609–610:281–87. Trans Tech Publications, Ltd., n.d. https://doi.org/10.4028/www.scientific.net/kem.609-610.281.
       Full Text
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