Hai "Helen" Li | Scholars@Duke

Hai "Helen" Li
Associate Professor in the Department of Electrical and Computer Engineering

Research Interests:
Brain-inspired computing systems, neuromorphic design
Memory design and architecture based on conventional and emerging technologies
Device/circuit/architecture co-design for low power and high performance

Office Hours

Appointment by email hai.li@duke.edu

Current Appointments & Affiliations

Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017

Contact Information

Rm103 Hudson Hall, 100 Science Dr., Durham, NC 27701
Rm130 Hudson Hall, Box 90291, Durham, NC 27701
hai.li@duke.edu (919) 660-1373
Google Scholar
Personal page

Background
Education, Training, & Certifications
- Ph.D., Purdue University 2004
Duke Appointment History
- Adjunct Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2016
Recognition
In the News
- JAN 3, 2017
  
  Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain
Awards & Honors
Research
Selected Grants
- SPX: Collaborative Research: Ula! - An Integrated DNN Acceleration Framework with Enhanced Unsupervised Learning Capability awarded by National Science Foundation 2017 - 2021
- The Controller Design and Integration of Memristor-based Neuromorphic System awarded by Air Force Research Laboratory 2018 - 2021
- CSR: SMALL: Collaborative Research: GAMBIT: Efficient Graph Processing on a Memristor-based Embedded Computing Platform awarded by National Science Foundation 2017 - 2020
- SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms awarded by Department of Energy 2017 - 2020
- SHF:Small: Cross-Platform Solutions for Pruning and Accelerating Neural Models awarded by National Science Foundation 2017 - 2019
- Scalable Event-driven Neuromorphic Learning Mechanics for Human-centric Computing awarded by Intel Corporation 2017 - 2018
- NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains awarded by National Science Foundation 2017 - 2018
- Planning IUCRC Duke University: Center for Alternative Sustainable and Intelligent Computing awarded by National Science Foundation 2017 - 2018
- The Design of Neuromorphic Controller System Built with Memristor Crossbars awarded by University of Pittsburgh 2017
Publications & Artistic Works
Selected Publications
- Books
  - Li, H, and Chen, Y. Nonvolatile Memory Design Magnetic, Resistive, and Phase Change. CRC Press, December 19, 2011.
- Book Sections
  - Li, Z, Liu, C, Li, H, and Chen, Y. "Neuromorphic hardware acceleration enabled by emerging technologies." In Emerging Technology and Architecture for Big-data Analytics, 217-244. April 19, 2017. Full Text
  - Chen, YC, Wang, Y, Zhang, W, Chen, Y, and Li, HH. "In-place logic obfuscation for emerging nonvolatile FPGAs." In Fundamentals of IP and SoC Security: Design, Verification, and Debug, 277-293. January 1, 2017. Full Text
  - Li, HH, Hu, M, and Liu, B. "Memristor modeling - static, statistical, and stochastic methodologies." In Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, 313-335. January 1, 2016. Full Text
  - Zhang, Y, Wen, W, Li, H, and Chen, Y. "The Prospect of STT-RAM Scaling." In Metallic Spintronic Devices. CRC Press, August 4, 2014. (Chapter)
  - Chen, Y, Li, H, and Sun, Z. "Spintronic memristor as interface between DNA and solid state devices." In Memristors and Memristive Systems, 281-298. August 1, 2014. Full Text
  - Li, H, Sun, Z, Bi, X, Wong, WF, Zhu, X, and Wu, W. "STT-RAM cache hierarchy design and exploration with emerging magnetic devices." In Emerging Memory Technologies: Design, Architecture, and Applications, 169-199. January 1, 2014. Full Text
  - Chen, Y, Li, H, Xie, Y, and Niu, D. "Low Power Design of Emerging Memory Technologies." In Handbook of Energy-aware and Green Computing. CRC Press, 2012. (Chapter)
  - Li, HH, Hu, M, and Pino, RE. "Statistical memristor model and its applications in neuromorphic computing." In Advances in Neuromorphic Memristor Science and Applications, 107-131. January 1, 2012. Full Text
  - Li, H, Chen, Y, and Jamshidi, S. "Design for Low Power." In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, January 7, 2008. (Chapter)
- Conference Papers
  - Hassan, AM, Li, HH, and Chen, Y. "Hardware implementation of echo state networks using memristor double crossbar arrays." June 30, 2017. Full Text
  - Li, S, Wen, W, Wang, Y, Han, S, Chen, Y, and Li, HH. "An FPGA design framework for CNN sparsification and acceleration." June 30, 2017. Full Text
  - Niu, D, Xue, R, Cai, T, Li, H, Effah, K, and Zhang, H. "The new large-scale RNNLM system based on distributed neuron." June 30, 2017. Full Text
  - Liu, C, Hu, M, Strachan, JP, and Li, HH. "Rescuing Memristor-based Neuromorphic Design with High Defects." June 18, 2017. Full Text
  - Wang, Y, Wen, W, Liu, B, Chiarulli, D, and Li, HH. "Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks." June 18, 2017. Full Text
  - Cheng, HP, Wen, W, Wu, C, Li, S, Li, H, and Chen, Y. "Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective." May 11, 2017. Full Text
  - Hassan, AM, Yang, C, Liu, C, Li, H, and Chen, Y. "Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays." May 11, 2017. Full Text
  - Song, L, Qian, X, Li, H, and Chen, Y. "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning." May 5, 2017. Full Text
  - Cline, BT, Heinrich-Barna, S, Wright, PJ, Li, H, Viswanath, V, Hu, S, Wesling, P, Qu, G, Ghosh, S, and Iranmanesh, AA. "Welcome." May 2, 2017. Full Text
  - Liu, C, Yang, Q, Zhang, C, Jiang, H, Wu, Q, and Li, H. "A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications." February 16, 2017. Full Text
  - Min, C, Guo, J, Li, H, and Chen, Y. "Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer." February 16, 2017. Full Text
  - Wang, Y, Wen, W, Song, L, and Li, H. "Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses." February 16, 2017. Full Text
  - Li, HH, Ghosal, P, and Theocharides, T. "Message from the Technical Program Chairs." January 23, 2017. Full Text
  - Li, H, and IEEE, . "Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies." 2017. Link to Item
  - Yan, B, Li, Z, Chen, Y, and Li, H. "RAM and TCAM designs by using STT-MRAM." December 9, 2016. Full Text
  - Song, C, Liu, B, Liu, C, Li, H, and Chen, Y. "Design techniques of eNVM-enabled neuromorphic computing systems." November 22, 2016. Full Text
  - Liu, C, Chen, Y, and Li, H. "Neural processor design enabled by memristor technology." November 8, 2016. Full Text
  - Li, S, Wang, Y, Wen, W, Wang, Y, Chen, Y, and Li, H. "A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel." November 7, 2016. Full Text
  - Yang, C, Liu, B, Li, H, Chen, Y, Wen, W, Barnell, M, Wu, Q, and Rajendran, J. "Security of neuromorphic computing: Thwarting learning attacks using memristor's obsolescence effect." November 7, 2016. Full Text
  - Yang, C, Wu, C, Li, H, Chen, Y, Barnell, M, and Wu, Q. "Security challenges in smart surveillance systems and the solutions based on emerging nano-devices." November 7, 2016. Full Text
  - Wu, C, Cheng, HP, Li, S, Li, HH, and Chen, Y. "ApesNet: A pixel-wise efficient segmentation network." October 1, 2016. Full Text
  - Cheng, HP, Wen, W, Song, C, Liu, B, Li, H, and Chen, Y. "Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss." September 14, 2016. Full Text
  - Li, HH, and Li, X. "Message from the general chairs." September 2, 2016. Full Text
  - Liu, C, Yang, Q, Yan, B, Yang, J, Du, X, Zhu, W, Jiang, H, Wu, Q, Barnell, M, and Li, HH. "A memristor crossbar based computing engine optimized for high speed and accuracy." September 2, 2016. Full Text
  - Guo, J, Min, C, Cai, T, Li, H, and Chen, Y. "ObjNandSim: Object-based NAND flash device simulator." August 17, 2016. Full Text
  - Chakraborty, S, Joshi, S, Xia, Q, Li, H, Chen, Y, Jiang, H, Wu, Q, Barnell, M, and Yang, JJ. "Built-in selectors self-assembled into memristors." July 29, 2016. Full Text
  - Li, S, Liu, X, Mao, M, Li, HH, Chen, Y, Li, B, and Wang, Y. "Heterogeneous systems with reconfigurable neuromorphic computing accelerators." July 29, 2016. Full Text
  - Liu, B, Yang, C, Li, H, Chen, Y, Wu, Q, and Barnell, M. "Security of neuromorphic systems: Challenges and solutions." July 29, 2016. Full Text
  - Yan, B, Mahmoud, AM, Yang, JJ, Wu, Q, Chen, Y, and Li, HH. "A neuromorphic ASIC design using one-selector-one-memristor crossbar." July 29, 2016. Full Text
  - Mao, M, Wen, W, Liu, X, Hu, J, Wang, D, Chen, Y, and Li, H. "TEMP: Thread batch enabled memory partitioning for GPU." June 5, 2016. Full Text
  - Wen, W, Wu, C, Wang, Y, Nixon, K, Wu, Q, Barnell, M, Li, H, and Chen, Y. "A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip." June 5, 2016. Full Text
  - Eken, E, Bayram, I, Zhang, Y, Yan, B, Wu, W, Li, H, and Chen, Y. "Spin-hall assisted STT-RAM design and discussion." June 4, 2016. Full Text
  - Cline, B, Li, HH, Qu, G, Mukhopadhyay, S, Viswanath, V, Iranmanesh, AA, Wright, PJ, and Wesling, P. "WELCOME to ISQED 2016." May 25, 2016. Full Text
  - Yang, C, Liu, B, Wang, Y, Chen, Y, Li, H, Zhang, X, and Sun, G. "The applications of NVM technology in hardware security." May 18, 2016. Full Text
  - Wang, X, Mao, M, Eken, E, Wen, W, Li, H, and Chen, Y. "Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache." April 25, 2016.
  - Wen, W, Mao, M, Li, H, Chen, Y, Pei, Y, and Ge, N. "A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations." April 25, 2016.
  - Liu, B, Liu, X, Liu, C, Wen, W, Meng, M, Li, H, and Chen, Y. "Hardware acceleration for neuromorphic computing: An evolving view." April 20, 2016. Full Text
  - Zhang, X, Guangyu, S, Zhang, Y, Chen, Y, Li, H, Wen, W, and Di, J. "A novel PUF based on cell error rate distribution of STT-RAM." March 7, 2016. Full Text
  - Li, H, Bi, X, and Sun, Z. "The evolutionary spintronic technologies and their usage in high performance computing." February 12, 2016. Full Text
  - Cline, B, Mukhopadhyay, S, Wright, PJ, Li, H, Viswanath, V, Wesling, P, Qu, G, and Iranmanesh, A. "Welcome." IEEE, 2016. Full Text
  - Guo, J, Liu, C, and Poignet, P. "Effect of Non-passive Operator on Enhanced Wave-Based Teleoperator for Robotic-Assisted Surgery: First Case Study." 2016. Full Text Link to Item
  - Li, H-Q, Liu, Q-W, Fang, J-S, and Wang, Y-L. "Synthesis and Characterization of 3-butyryloxy-16-(beta-naphthylmethylene)-5 alpha-androstane-17-one." 2016. Link to Item
  - Wen, W, Wu, C, Wang, Y, Chen, Y, and Li, H. "Learning structured sparsity in deep neural networks." January 1, 2016.
  - Liang, H, Chen, YC, Luo, T, Zhang, W, Li, H, and He, B. "Hierarchical Library Based Power Estimator for Versatile FPGAs." November 11, 2015. Full Text
  - Li, Z, Liu, C, Wang, Y, Yan, B, Yang, C, Yang, J, and Li, H. "An overview on memristor crossabr based neuromorphic circuit and architecture." October 30, 2015. Full Text
  - Liang, H, Zhang, W, Sinha, S, Chen, YC, and Li, H. "Hierarchical library based power estimator for versatile FPGAs." October 7, 2015. Full Text
  - Li, HH, Liu, C, Yan, B, Yang, C, Song, L, Li, Z, Chen, Y, Zhu, W, Wu, Q, and Jiang, H. "Spiking-based matrix computation by leveraging memristor crossbar array." August 17, 2015. Full Text
  - Wang, Y, Tang, T, Xia, L, Li, B, Gu, P, Li, H, Xie, Y, and Yang, H. "Energy efficient RRAM spiking neural network for real time classification." May 20, 2015. Full Text
  - Wang, Y, Wen, W, Hu, M, and Li, H. "A novel true random number generator design leveraging emerging memristor technology." May 20, 2015. Full Text
  - Yan, B, Li, Z, Zhang, Y, Yang, J, Zhao, W, Chia, PCF, and Li, H. "A high-speed robust NVM-TCAM design using body bias feedback." May 20, 2015. Full Text
  - Eken, E, Zhang, Y, Yan, B, Wu, W, Li, H, and Chen, Y. "Spin-hall assisted STT-RAM design and discussion." January 1, 2015. Full Text
  - Guo, J, Wen, W, Hu, J, Wang, D, Li, H, and Chen, Y. "FlexLevel: A novel NAND flash storage system design for LDPC latency reduction." January 1, 2015. Full Text
  - Li, H, Liu, B, Liu, X, Mao, M, Chen, Y, Wu, Q, and Qiu, Q. "The applications of memristor devices in next-generation cortical processor designs." January 1, 2015. Full Text
  - Li, H, Liu, X, Mao, M, Chen, Y, Wu, Q, and Barnell, M. "Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper)." January 1, 2015. Full Text
  - Li, S, Wu, C, Li, H, Li, B, Wang, Y, and Qiu, Q. "FPGA acceleration of recurrent neural network based language model." January 1, 2015. Full Text
  - Li, Z, Yan, B, Yang, L, Zhao, W, Chen, Y, and Li, H. "A new self-reference sensing scheme for TLC MRAM." January 1, 2015. Full Text
  - Liu, B, Li, H, Chen, Y, Li, X, Huang, T, Wu, Q, and Barnell, M. "Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems." January 1, 2015. Full Text
  - Liu, B, Li, H, Chen, Y, Li, X, Wu, Q, and Huang, T. "Vortex: Variation-aware training for memristor X-bar." January 1, 2015. Full Text
  - Liu, B, Wu, C, Li, H, Chen, Y, Wu, Q, Barnell, M, and Qiu, Q. "Cloning your mind: Security challenges in cognitive system designs and their solutions." January 1, 2015. Full Text
  - Liu, C, Yan, B, Yang, C, Song, L, Li, Z, Liu, B, Chen, Y, Li, H, Wu, Q, and Jiang, H. "A spiking neuromorphic design with resistive crossbar." January 1, 2015. Full Text
  - Liu, X, Mao, M, Bi, X, Li, H, and Chen, Y. "An efficient STT-RAM-based register file in GPU architectures." January 1, 2015. Full Text
  - Liu, X, Mao, M, Liu, B, Li, H, Chen, Y, Li, B, Wang, Y, Jiang, H, Barnell, M, Wu, Q, and Yang, J. "RENO: A high-efficient reconfigurable neuromorphic computing accelerator design." January 1, 2015. Full Text
  - Mao, M, Hu, J, Chen, Y, and Li, H. "VWS: A versatile warp scheduler for exploring diverse cache localities of GPGPU applications." January 1, 2015. Full Text
  - Tang, T, Luo, R, Li, B, Li, H, Wang, Y, and Yang, H. "Energy efficient spiking neural network design with RRAM devices." January 1, 2015. Full Text
  - Wang, Y-Y, He, L-B, Zhu, H-J, and Yang, P. "CONSISTENCY OF SURFACE PULSE AND RECIPROCITY CALIBRATION OF PIEZOELECTRIC AE SENSORS." 2015. Link to Item
  - Wright, PJ, Raychowdhury, A, Liu, B, Mukhopadhyay, S, Li, HH, Iranmanesh, AA, Alam, SM, and Wesling, P. "Welcome to ISQED 2015." January 1, 2015. Full Text
  - Zhang, C, Sun, G, Zhang, W, Mi, F, Li, H, and Zhao, W. "Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power." January 1, 2015. Full Text
  - Zhang, Y, Yan, B, Wu, W, Li, H, and Chen, Y. "Giant spin hall effect (GSHE) logic design for low power application." January 1, 2015.
  - Chen, L, Li, C, Huang, T, He, X, Li, H, and Chen, Y. "STDP learning rule based on memristor with STDP property." September 3, 2014. Full Text
  - Hu, M, Wang, Y, Qiu, Q, Chen, Y, and Li, H. "The stochastic modeling of TiO2memristor and its usage in neuromorphic system design." March 27, 2014. Full Text
  - Wang, J, Tim, Y, Wong, WF, Ong, ZL, Sun, Z, and Li, HH. "A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores." March 27, 2014. Full Text
  - Liu, X, Mao, M, Li, H, Chen, Y, Jiang, H, Yang, JJ, Wu, Q, and Barnell, M. "A heterogeneous computing system with memristor-based neuromorphic accelerators." February 11, 2014. Full Text
  - Cavallaro, JR, Zhang, T, Jones, AK, and Li, H. "GLSVLSI'14 chairs' welcome." January 1, 2014.
  - Eken, E, Zhang, Y, Wen, W, Joshi, R, Li, H, and Chen, Y. "A new field-assisted access scheme of STT-RAM with self-reference capability." January 1, 2014. Full Text
  - Hu, X, Feng, G, Li, H, Chen, Y, and Duan, S. "An adjustable memristor model and its application in small-world neural networks." January 1, 2014. Full Text
  - Li, B, Wang, Y, Chen, Y, Li, HH, and Yang, H. "ICE: Inline calibration for memristor crossbar-based computing engine." January 1, 2014. Full Text
  - Li, H, Hu, M, Li, C, and Duan, S. "Memristor modeling - Static, statistical, and stochastic methodologies." January 1, 2014. Full Text
  - Li, H, Hu, M, Liu, X, Mao, M, Li, C, and Duan, S. "Emerging memristor technology enabled next generation cortical processor." January 1, 2014. Full Text
  - Liu, C, and Li, H. "A weighted sensing scheme for ReRAM-based cross-point memory array." January 1, 2014. Full Text
  - Mao, M, Wen, W, Zhang, Y, Chen, Y, and Li, H. "Exploration of GPGPU register file architecture using domain-wall-shift- write based racetrack memory." January 1, 2014. Full Text
  - Park, E, Yoo, S, Lee, S, and Li, H. "Accelerating graph computation with racetrack memory and pointer-assisted graph representation." January 1, 2014. Full Text
  - Qiu, Q, Li, Z, Ahmed, K, Li, HH, and Hu, M. "Neuromorphic acceleration for context aware text image recognition." January 1, 2014. Full Text
  - Sun, Z, Bi, X, Jones, AK, Li, H, Sun, Z, Bi, X, Jones, AK, and Li, H. "Design exploration of racetrack lower-level cachesDesign exploration of racetrack lower-level caches (PublishedPublished)." January 1, 2014. Full Text
  - Wang, J, Roy, P, Wong, W-F, Bi, X, Li, HH, and IEEE, . "Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration." 2014. Link to Item
  - Wang, J, Roy, P, Wong, WF, Bi, X, and Li, H. "Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration." January 1, 2014. Full Text
  - Wu, Q, Liu, B, Chen, Y, Li, H, Chen, Q, and Qiu, Q. "Bio-inspired computing with resistive memories - Models, architectures and applications." January 1, 2014. Full Text
  - Ying, C, Peng, L, and Zhiwu, Y. "Research on the sol-gel method of preparing ternary nano SiO2-Al2O3-TiO2 materials." 2014. Full Text Link to Item
  - Wang, J, Tim, Y, Wong, WF, and Li, HH. "A practical low-power memristor-based analog neural branch predictor." December 11, 2013. Full Text
  - Bi, X, Mao, M, Wang, D, and Li, H. "Unleashing the potential of MLC STT-RAM caches." December 1, 2013. Full Text
  - Chen, Q, Qiu, Q, Li, H, and Wu, Q. "A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring." December 1, 2013. Full Text
  - Ji, F, Li, HH, Wysocki, B, Thiem, C, and McDonald, N. "Memristor-based synapse design and a case study in reconfigurable systems." December 1, 2013. Full Text
  - Zhang, Y, Bayram, I, Wang, Y, Li, H, and Chen, Y. "ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications." December 1, 2013. Full Text
  - Chen, Z, Zhang, L, Bi, X, and Li, H. "A pseudo-weighted sensing scheme for memristor based cross-point memory." November 6, 2013. Full Text
  - Bi, X, Weldon, MA, and Li, H. "STT-RAM designs supporting dual-port accesses." October 21, 2013.
  - Guo, J, Wen, W, Li, YZ, Li, S, Li, H, and Chen, Y. "DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems." October 21, 2013.
  - Hu, M, Li, H, Chen, Y, Wu, Q, and Rose, GS. "BSB training scheme implementation on memristor-based circuit." October 9, 2013. Full Text
  - Liu, B, Hu, M, Li, H, Mao, ZH, Chen, Y, Huang, T, and Zhang, W. "Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine." July 12, 2013. Full Text
  - Sun, Z, Wu, W, and Li, H. "Cross-layer racetrack memory design for ultra high density and low power consumption." July 12, 2013. Full Text
  - Mao, M, Li, H, Jones, AK, and Chen, Y. "Coordinating prefetching and STT-RAM based last-level cache management for multicore systems." May 30, 2013. Full Text
  - Chen, YC, Zhang, W, and Li, HH. "A hardware security scheme for RRAM-based FPGA." January 1, 2013. Full Text
  - Li, H-J, Xie, Z-G, and Hu, W. "An Image Compression Method using Sparse Representation and Grey Relation." 2013. Link to Item
  - Chen, YC, Wang, W, Li, H, and Zhang, W. "Non-volatile 3D stacking RRAM-based FPGA." December 12, 2012. Full Text
  - Chen, YC, Wang, W, Zhang, W, and Li, H. "uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology." December 1, 2012. Full Text
  - Bi, X, Li, H, and Kim, JJ. "Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design." October 29, 2012. Full Text
  - Chen, YC, Li, H, and Zhang, W. "A novel peripheral circuit for RRAM-based LUT." September 28, 2012. Full Text
  - Hu, M, Li, H, Wu, Q, Rose, GS, and Chen, Y. "Memristor crossbar based hardware realization of BSB recall function." August 22, 2012. Full Text
  - Wang, H, Li, H, and Pino, RE. "Memristor-based synapse design and training scheme for neuromorphic computing architecture." August 22, 2012. Full Text
  - Hu, M, Li, H, Wu, Q, and Rose, GS. "Hardware realization of BSB recall function using memristor crossbar arrays." July 11, 2012. Full Text
  - Pino, RE, Li, H, Chen, Y, Hu, M, and Liu, B. "Statistical memristor modeling and case study in neuromorphic computing." July 11, 2012. Full Text
  - Bi, X, Zhang, C, Li, H, Chen, Y, and Pino, RE. "Spintronic memristor based temperature sensor design with CMOS current reference." May 24, 2012.
  - Zhao, B, Yang, J, Zhang, Y, Chen, Y, and Li, H. "Architecting a common-source-line array for bipolar non-volatile memory devices." May 24, 2012.
  - Chen, X, Zeng, J, Chen, Y, Zhang, W, and Li, H. "Fine-grained dynamic voltage scaling on OLED display." April 26, 2012. Full Text
  - Chen, YC, Zhang, W, and Li, H. "A look up table design with 3D bipolar RRAMs." April 26, 2012. Full Text
  - Bi, X, Sun, Z, Li, H, Wu, W, and IEEE, . "Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches." 2012. Link to Item
  - Hu, M, Li, H, and Pino, RE. "Fast statistical model of TiO2thin-film memristor and design implication." December 1, 2011. Full Text
  - Joshi, R, Kanj, R, Wang, P, and Li, HH. "Universal statistical cure for predicting memory loss." December 1, 2011. Full Text
  - Sun, Z, Bi, X, Li, H, Wong, WF, Ong, ZL, Zhu, X, and Wu, W. "Multi retention level STT-RAM cache designs with a dynamic refresh scheme." December 1, 2011. Full Text
  - Xue, CJ, Zhang, Y, Chen, Y, Sun, G, Yang, JJ, and Li, H. "Emerging non-volatile memories: Opportunities and challenges." November 22, 2011. Full Text
  - Wang, P, Chen, X, Chen, Y, Li, H, Kang, S, Zhu, X, and Wu, W. "A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis." November 9, 2011. Full Text
  - Chen, Y, Wong, WF, Li, H, and Koh, CK. "Processor caches built using multi-level spin-transfer torque RAM cells." September 19, 2011. Full Text
  - Chen, YC, Li, H, Zhang, W, and Pino, RE. "3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design." August 11, 2011. Full Text
  - Chen, YC, Li, H, Chen, Y, and Pino, RE. "3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers." May 31, 2011.
  - Chen, Y, and Li, H. "Emerging sensing techniques for emerging memories." March 28, 2011. Full Text
  - Hu, M, Li, H, Chen, Y, Wang, X, and Pino, RE. "Geometry variations analysis of TiO2thin-film and spintronic memristors." March 28, 2011. Full Text
  - Joshi, R, Kanj, R, Wang, P, Li, HH, and IEEE, . "Universal Statistical Cure For Predicting Memory Loss (Invited Paper)." 2011. Link to Item
  - Sun, Z, Li, H, Chen, Y, and Wang, X. "Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement." December 1, 2010. Full Text
  - Chen, Y, Wang, X, Zhu, W, Li, H, Sun, Z, Sun, G, and Xie, Y. "Access scheme of multi-level cell spin-transfer torque random access memory and its optimization." September 20, 2010. Full Text
  - Li, H, and Chen, Y. "Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture." September 20, 2010. Full Text
  - Chen, Y, Li, H, Wang, X, Zhu, W, Xu, W, and Zhang, T. "A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)." June 9, 2010.
  - Li, H, and Hu, M. "Compact model of memristors and its application in computing systems." June 9, 2010.
  - Chen, Y, Tian, W, Li, H, Wang, X, and Zhu, W. "Scalability of PCMO-based resistive switch device in DSM technologies." May 28, 2010. Full Text
  - Koh, CK, Wong, WF, Chen, Y, and Li, H. "The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies." December 1, 2009. Full Text
  - Li, H, Xi, H, Chen, Y, Stricklin, J, Wang, X, and Zhang, T. "Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration." October 5, 2009. Full Text
  - Li, H, Chen, Y, and IEEE, . "An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures." 2009. Link to Item
  - Dong, X, Wu, X, Sun, G, Xie, Y, Li, H, and Chen, Y. "Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement." September 17, 2008. Full Text
  - Chen, Y, Wang, X, Li, H, Liu, H, Dimitrov, DV, and IEEE, . "Design margin exploration of spin-torque transfer RAM (SPRAM)." 2008. Full Text Link to Item
  - Chen, Y, Li, H, Li, J, and Koh, CK. "Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI." December 17, 2007. Full Text
  - Wong, WF, Kon, CK, Chen, Y, and Li, H. "VOSCH: Voltage scaled cache hierarchies." December 1, 2007. Full Text
  - Li, H, Chen, Y, Roy, K, and Koh, CK. "SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design." September 19, 2006.
  - Chen, Y, Li, H, Roy, K, and Koh, CK. "Cascaded carry-select adder (C²SA): A new structure for low-power CSA design." December 12, 2005.
  - Chen, YR, Li, H, Roy, K, Koh, CK, and IEEE, . "Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies." 2005. Link to Item
  - Li, H, Bhunia, S, Chen, YR, Roy, K, and Vijaykumar, TN. "DCG: Deterministic clock-gating for low-power microprocessor design." March 2004. Full Text Link to Item
  - Li, H, Bhunia, S, Chen, Y, Vijaykumar, TN, and Roy, K. "Deterministic clock gating for microprocessor power reduction." January 1, 2003. Full Text
  - Li, H, Cher, CY, Vijaykumar, TN, Roy, K, and SOCIETY, IC. "VSV: L2-miss-driven variable supply-voltage scaling for low power." 2003. Link to Item
  - Agarwal, A, Li, H, Roy, K, ACM, , ACM, , and ACM, . "DRG-cache: A data retention gated-ground cache for low power." 2002. Link to Item
  - Bhunia, S, Li, H, Roy, K, SOCIETY, IC, and SOCIETY, IC. "A high performance IDDQ testable cache for scaled CMOS technologies." 2002. Full Text Link to Item
- Journal Articles
  - Wang, D, Ma, L, Zhang, M, An, J, Li, HH, and Chen, Y. "Shift-Optimized Energy-Efficient Racetrack-Based Main Memory (Accepted)." Journal of Circuits, Systems and Computers 27, no. 05 (May 2018): 1850081-1850081. Full Text
  - Mao, M, Wen, W, Zhang, Y, Chen, Y, and Li, H. "An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory." IEEE Transactions on Computers 66, no. 9 (September 1, 2017): 1478-1490. Full Text
  - Hu, M, Chen, Y, Yang, JJ, Wang, Y, and Li, HH. "A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 8 (August 2017): 1353-1366. Full Text
  - Guo, J, Wen, W, Hu, J, Wang, D, Li, H, and Chen, Y. "FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 7 (July 2017): 1167-1180. Full Text
  - Bi, X, Mao, M, Wang, D, and Li, HH. "Cross-Layer Optimization for Multilevel Cell STT-RAM Caches." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 6 (June 2017): 1807-1820. Full Text
  - Chen, Y, Li, HH, Bayram, I, and Eken, E. "Recent Technology Advances of Emerging Memories." IEEE Design & Test 34, no. 3 (June 2017): 8-22. Full Text
  - Eken, E, Bayram, I, Zhang, Y, Yan, B, Wu, W, Li, HH, and Chen, Y. "Giant Spin-Hall assisted STT-RAM and logic design." Integration, the VLSI Journal 58 (June 2017): 253-261. Full Text
  - MOHANTY, SP, LI, X, LI, H, and CAO, Y. "Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing." IEEE Transactions on Nanotechnology 16, no. 3 (May 2017): 383-386. Full Text
  - Li, HH, Chen, Y, Liu, C, Strachan, JP, and Davila, N. "Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing." IEEE Consumer Electronics Magazine 6, no. 1 (January 2017): 94-103. Full Text
  - Wu, C, Cheng, H-P, Li, S, Li, HH, and Chen, Y. "ApesNet: a pixel-wise efficient segmentation network for embedded devices ." IET Cyber-Physical Systems: Theory & Applications 1, no. 1 (December 1, 2016): 78-85. Full Text
  - Li, HH, Qiu, Q, and Wang, Y. "Guest Editorial: Design and Applications of Neuromorphic Computing System." IEEE Transactions on Multi-Scale Computing Systems 2, no. 4 (October 1, 2016): 223-224. Full Text
  - Qiu, Q, Li, Z, Ahmed, K, Liu, W, Habib, SF, Li, H, and Hu, M. "A Neuromorphic Architecture for Context Aware Text Image Recognition." Journal of Signal Processing Systems 84, no. 3 (September 2016): 355-369. Full Text
  - DeMara, R, Pyle, S, and Li, H. "Compact low-power instant store and restore D flip-flop using a self-complementing spintronic device." Electronics Letters 52, no. 14 (July 7, 2016): 1238-1240. Full Text
  - Hu, M, Wang, Y, Wen, W, Wang, Y, and Li, H. "Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 2016): 235-246. Full Text
  - Yang, J, Sun, Z, Wang, X, Chen, Y, and Li, H. "Spintronic Memristor as Interface Between DNA and Solid State Devices." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 2016): 212-221. Full Text
  - Mao, F, Chen, Y-C, Zhang, W, Li, HH, and He, B. "Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration." ACM Transactions on Design Automation of Electronic Systems 21, no. 4 (May 18, 2016): 1-26. Full Text
  - Duan, S, Dong, Z, Hu, X, Wang, L, and Li, H. "Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition." Neural Computing and Applications 27, no. 4 (May 2016): 837-844. Full Text
  - Liu, X, Mao, M, Liu, B, Li, B, Wang, Y, Jiang, H, Barnell, M, Wu, Q, Yang, J, Li, H, and Chen, Y. "Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 2016): 617-628. Full Text
  - Sun, Z, Bi, X, Wu, W, Yoo, S, and Li, HH. "Array Organization and Data Management Exploration in Racetrack Memory." IEEE Transactions on Computers 65, no. 4 (April 1, 2016): 1041-1054. Full Text
  - Yang, J, Wang, P, Zhang, Y, Cheng, Y, Zhao, W, Chen, Y, and Li, HH. "Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (March 2016): 380-393. Full Text
  - Zhang, Y, Li, Y, Sun, Z, Li, H, Chen, Y, and Jones, AK. "Read Performance: The Newest Barrier in Scaled STT-RAM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 6 (June 2015): 1170-1174. Full Text
  - Eken, E, Zhang, Y, Wen, W, Joshi, R, Li, H, and Chen, Y. "A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement." IEEE Transactions on Magnetics 50, no. 11 (November 2014): 1-4. Full Text
  - Hu, M, Li, H, Chen, Y, Wu, Q, Rose, GS, and Linderman, RW. "Memristor crossbar-based neuromorphic computing system: a case study." IEEE transactions on neural networks and learning systems 25, no. 10 (October 2014): 1864-1878. Full Text
  - Sun, Z, Bi, X, Li, H, Wong, W-F, and Zhu, X. "STT-RAM Cache Hierarchy With Multiretention MTJ Designs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 6 (June 2014): 1281-1293. Full Text
  - Dong, Z, Duan, S, Hu, X, Wang, L, and Li, H. "A novel memristive multilayer feedforward small-world neural network with its applications in PID control." The Scientific World Journal 2014 (January 2014): 394828-. Full Text
  - Li, Y, Zhang, Y, Li, H, Chen, Y, and Jones, AK. "C1C: A configurable, compiler-guided STT-RAM L1 cache." Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). Full Text
  - Zhao, B, Yang, J, Zhang, Y, Chen, Y, and Li, H. "Common-source-line array." ACM Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013): 1-18. Full Text
  - Chen, Y, Wong, W-F, Li, H, Koh, C-K, Zhang, Y, and Wen, W. "On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations." ACM Journal on Emerging Technologies in Computing Systems 9, no. 2 (May 1, 2013): 1-22. Full Text
  - Li, Y, Zhang, Y, Li, H, Chen, Y, and Jones, AK. "C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache." ACM Transactions on Architecture and Code Optimization 10, no. 4 (January 1, 2013): 1-22. Full Text
  - Bi, X, Li, H, and Wang, X. "STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence." IEEE Transactions on Magnetics 48, no. 11 (November 2012): 3821-3824. Full Text
  - Sun, Z, Li, H, Chen, Y, and Wang, X. "Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 11 (November 2012): 2020-2030. Full Text
  - Chen, Y-C, Li, H, Zhang, W, and Pino, RE. "The 3-D Stacking Bipolar RRAM for High Density." IEEE Transactions on Nanotechnology 11, no. 5 (September 2012): 948-956. Full Text
  - LI, HH, and SUN, Z. "VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT." SPIN 02, no. 03 (September 2012): 1240008-1240008. Full Text
  - Sun, Z, Chen, X, Zhang, Y, Li, H, and Chen, Y. "Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder." ACM Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012): 1-16. Full Text
  - Sun, Z, Li, H, and Wang, X. "Magnetic tunnel junction design margin exploration for self-reference sensing scheme." Journal of applied physics 111, no. 7 (April 2012): 7C726-7C7263. Full Text
  - Chen, Y, Li, H, Wang, X, Zhu, W, Xu, W, and Zhang, T. "A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme." IEEE Journal of Solid-State Circuits 47, no. 2 (February 2012): 560-573. Full Text
  - Wang, H, Megill, A, He, K, Kirkwood, A, and Lee, H-K. "Consequences of Inhibiting Amyloid Precursor Protein Processing Enzymes on Synaptic Function and Plasticity." Neural Plasticity 2012 (2012): 1-24. Full Text
  - Li, H, Wang, X, Ong, Z-L, Wong, W-F, Zhang, Y, Wang, P, and Chen, Y. "Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement." IEEE Transactions on Magnetics 47, no. 10 (October 2011): 2356-2359. Full Text
  - Wang, P, Wang, X, Zhang, Y, Li, H, Levitan, SP, and Chen, Y. "Nonpersistent Errors Optimization in Spin-MOS Logic and Storage Circuitry." IEEE Transactions on Magnetics 47, no. 10 (October 2011): 3860-3863. Full Text
  - Zhang, Y, Wang, X, Li, H, and Chen, Y. "STT-RAM Cell Optimization Considering MTJ and CMOS Variations." IEEE Transactions on Magnetics 47, no. 10 (October 2011): 2962-2965. Full Text
  - Hu, M, Li, HH, Chen, Y, and Wang, X. "Spintronic Memristor: Compact Model and Statistical Analysis." Journal of Low Power Electronics 7, no. 2 (April 1, 2011): 234-244. Full Text
  - Dong, X, Wu, X, Xie, Y, Chen, Y, and Li, H. "Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation." IET Computers & Digital Techniques 5, no. 3 (2011): 213-213. Full Text
  - Zhu, W, Li, H, Chen, Y, and Wang, X. "Current Switching in MgO-Based Magnetic Tunneling Junctions." IEEE Transactions on Magnetics 47, no. 1 (January 2011): 156-160. Full Text
  - Chen, Y, Wang, X, Li, H, Xi, H, Yan, Y, and Zhu, W. "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 12 (December 2010): 1724-1734. Full Text
  - Chen, Y, Li, H, Koh, C-K, Sun, G, Li, J, Xie, Y, and Roy, K. "Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 11 (November 2010): 1621-1624. Full Text
  - Yiran Chen, , Wei Tian, , Hai Li, , Xiaobin Wang, , and Wenzhong Zhu, . "PCMO Device With High Switching Stability." IEEE Electron Device Letters 31, no. 8 (August 2010): 866-868. Full Text
  - Haiwen Xi, , Stricklin, J, Hai Li, , Yiran Chen, , Xiaobin Wang, , Yuankai Zheng, , Zheng Gao, , and Tang, M. "Spin Transfer Torque Memory With Thermal Assist Mechanism: A Case Study." IEEE Transactions on Magnetics 46, no. 3 (March 2010): 860-865. Full Text
  - Xiaobin Wang, , Yiran Chen, , Ying Gu, , and Hai Li, . "Spintronic Memristor Temperature Sensor." IEEE Electron Device Letters 31, no. 1 (January 2010): 20-22. Full Text
  - Yiran Chen, , Hai Li, , Roy, K, and Cheng-Kok Koh, . "Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 12 (December 2009): 1749-1752. Full Text
  - Koh, C-K, Wong, W-F, Chen, Y, and Li, H. "Tolerating process variations in large, set-associative caches." ACM Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009): 1-34. Full Text
  - Xiaobin Wang, , Yiran Chen, , Haiwen Xi, , Hai Li, , and Dimitrov, D. "Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion." IEEE Electron Device Letters 30, no. 3 (March 2009): 294-297. Full Text
  - Xiaobin Wang, , Yiran Chen, , Hai Li, , Dimitrov, D, and Liu, H. "Spin Torque Random Access Memory Down to 22 nm Technology." IEEE Transactions on Magnetics 44, no. 11 (November 2008): 2479-2482. Full Text
  - Hai Li, , Chen-Yong Cher, , Roy, K, and Vijaykumar, T. "Combined circuit and architectural level variable supply-voltage scaling for low power." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 5 (May 2005): 564-576. Full Text
  - Hai Li, , Bhunia, S, Yiran Chen, , Roy, K, and Vijaykumar, T. "DCG: deterministic clock-gating for low-power microprocessor design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 3 (March 2004): 245-254. Full Text
  - Agarwal, A, Hai Li, , and Roy, K. "A single-V/sub t/ low-leakage gated-ground cache for deep submicron." IEEE Journal of Solid-State Circuits 38, no. 2 (February 2003): 319-328. Full Text
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