Scholars@Duke

• Background
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  Education, Training, & Certifications

  • Ph.D., Purdue University 2004
• 

  Duke Appointment History

  • Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017 - 2020
  • Associate Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2018 - 2020
  • Adjunct Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2016
• Recognition
• 

  In the News

  • JAN 3, 2017

    Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain
• 

  Awards & Honors

  • Best Paper Award for the paper titled “Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2017
  • Fulton C. Noss Faculty Fellow. University of Pittsburgh. 2016
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2015
  • Best Paper Award for the paper titled “Quantitative Modeling of Racetrack Memory - A Tradeoff among Area, Performance, and Power”. Asia and South Pacific Design Automation Conference (ASPDAC). January 2015
  • Best Paper Award for the paper titled “A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI). July 2014
  • Best Paper Award for the paper titled “Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems”. Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI). April 2013
  • Air Force Visiting Faculty Research Program (VFRP) Fellowship. AFRL/RIB. 2013
  • DARPA Young Faculty Award. Defense Advanced Research Projects Agency (DARPA). 2013
  • NSF Career Award. National Science Foundation (NSF). 2012
  • Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2011
  • Best Paper Award for the paper titled “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM”. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED). August 2010
  • Best Paper Award for the paper titled “Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)”. the 9th International Symposium on Quality Electronic Design (ISQED). March 2008
• Research
• 

  Selected Grants

  • Collaborative Research: ASCENT: 3D memristor convolutional kernels with diffusive memristor based reservoir for real-time machine learning awarded by University of Massachusetts - Amherst 2020 - 2024
  • IUCRC Proposal Phase 1 Duke: Center for Alternative Sustainable and Intelligent Computing (ASIC) awarded by  National Science Foundation 2018 - 2023
  • Collaborative Research: CNS Core: Medium: Exploiting Synergies between Machine learning algorithms and hardware heterogeneity for high-performance and Reliable Manycore Computing Platforms awarded by  National Science Foundation 2020 - 2023
  • FET: Small:RESONANCE:Accelerating Speech/Language Processing through Collective Training using Commodity ReRAM Chips awarded by  National Science Foundation 2019 - 2022
  • A Hardware and Software Co-design Framework for Energy Efficient Neuromorphic Systems awarded by Department of Energy 2020 - 2022
  • SPX: Collaborative Research: Ula! - An Integrated DNN Acceleration Framework with Enhanced Unsupervised Learning Capability awarded by  National Science Foundation 2017 - 2022
  • Neural-Network Enhanced Radar Surveillance (NNERS) awarded by Defense Advanced Research Projects Agency 2020 - 2021
  • The Controller Design and Integration of Memristor-based Neuromorphic System awarded by Air Force Research Laboratory 2018 - 2021
  • NSF Convergence Accelerator Track D: A Trusted Integrative Model and Data Sharing Platform for Accelerating AI-Driven Health Innovation awarded by  National Science Foundation 2020 - 2021
  • Quantifying Ensemble Diversity for Robust Machine Learning (QED RML) awarded by Radiance Technologies, Inc. 2019 - 2021
  • CSR: SMALL: Collaborative Research: GAMBIT: Efficient Graph Processing on a Memristor-based Embedded Computing Platform awarded by  National Science Foundation 2017 - 2020
  • Scalable Event-driven Neuromorphic Learning Mechanics for Human-centric Computing awarded by Intel Corporation 2017 - 2020
  • Reverse Engineering of Deceptions (RED) awarded by Radiance Technologies, Inc. 2019 - 2020
  • SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms awarded by Department of Energy 2017 - 2020
  • Systematically Studying Backdoor Attacks on DNNs and Developing a Detection Architecture awarded by Army Research Office 2019
  • SHF:Small: Cross-Platform Solutions for Pruning and Accelerating Neural Models awarded by  National Science Foundation 2017 - 2019
  • NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains awarded by  National Science Foundation 2017 - 2018
  • Planning IUCRC Duke University: Center for Alternative Sustainable and Intelligent Computing awarded by  National Science Foundation 2017 - 2018
  • The Design of Neuromorphic Controller System Built with Memristor Crossbars awarded by University of Pittsburgh 2017
• 

  External Relationships

  • City University of Hong Kong
  • IEEE IEDM conference
  • Nanomatronix, LLC
  • National Tsing Hua University, Taiwan
  • NeoNexus Pte. Ltd.
  • Radiance Technologies, Inc.
• Publications & Artistic Works
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  Selected Publications

  • Books

    • Li, H., and Y. Chen. Nonvolatile memory design: Magnetic, resistive, and phase change, 2017. https://doi.org/10.1201/b11354.
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  • Academic Articles

    • Hu, W., C. H. Chang, A. Sengupta, S. Bhunia, R. Kastner, and H. Li. “An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 40, no. 6 (June 1, 2021): 1010–38. https://doi.org/10.1109/TCAD.2020.3047976.
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    • Joardar, B. K., J. R. Doppa, P. P. Pande, H. Li, and K. Chakrabarty. “AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 40, no. 5 (May 1, 2021): 971–84. https://doi.org/10.1109/TCAD.2020.3013194.
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    • Kim, B., E. Hanson, and H. Li. “An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks.” Ieee Transactions on Circuits and Systems Ii: Express Briefs 68, no. 5 (May 1, 2021): 1600–1604. https://doi.org/10.1109/TCSII.2021.3067840.
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    • Yang, Q., and H. Li. “BitSystolic: A 26.7 TOPS/W 2b8b NPU with Configurable Data Flows for Edge Devices.” Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 3 (March 1, 2021): 1134–45. https://doi.org/10.1109/TCSI.2020.3043778.
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    • Liang, F., Z. Tian, M. Dong, S. Cheng, L. Sun, H. Li, Y. Chen, and G. Zhang. “Efficient neural network using pointwise convolution kernels with linear phase constraint.” Neurocomputing 423 (January 29, 2021): 572–79. https://doi.org/10.1016/j.neucom.2020.10.067.
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    • Liu, X., M. Mao, X. Bi, H. Li, and Y. Chen. “Exploring Applications of STT-RAM in GPU Architectures.” Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (January 1, 2021): 238–49. https://doi.org/10.1109/TCSI.2020.3031895.
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    • Lan, Y., K. W. Nixon, Q. Guo, G. Zhang, Y. Xu, H. Li, and Y. Chen. “FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 12 (December 1, 2020): 4791–4804. https://doi.org/10.1109/TCAD.2020.2969982.
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    • Li, Z., B. Li, Z. Fan, and H. Li. “RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 12 (December 1, 2020): 4736–47. https://doi.org/10.1109/TCAD.2020.2981055.
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    • Serrano-Gotarredona, T., M. Valle, F. Conti, and H. Li. “Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020).” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 10, no. 4 (December 1, 2020): 403–5. https://doi.org/10.1109/JETCAS.2020.3040581.
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    • Yang, C., B. Liu, H. Li, Y. Chen, M. Barnell, Q. Wu, W. Wen, and J. Rajendran. “Thwarting Replication Attack against Memristor-Based Neuromorphic Computing System.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 10 (October 1, 2020): 2192–2205. https://doi.org/10.1109/TCAD.2019.2937817.
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    • Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, and H. Li. “Adversarial Attack: A New Threat to Smart Devices and How to Defend It.” Ieee Consumer Electronics Magazine 9, no. 4 (July 1, 2020): 49–55. https://doi.org/10.1109/MCE.2020.2969150.
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    • Zhang, G., B. Li, J. Wu, R. Wang, Y. Lan, L. Sun, S. Lei, H. Li, and Y. Chen. “A low-cost and high-speed hardware implementation of spiking neural network.” Neurocomputing 382 (March 21, 2020): 106–15. https://doi.org/10.1016/j.neucom.2019.11.045.
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    • Li, B., J. R. Doppa, P. P. Pande, K. Chakrabarty, J. X. Qiu, and H. H. Li. “3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.” Acm Journal on Emerging Technologies in Computing Systems 16, no. 2 (January 29, 2020). https://doi.org/10.1145/3375699.
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    • Li, B., M. Mao, X. Liu, T. Liu, Z. Liu, W. Wen, Y. Chen, and H. H. Li. “Thread batching for high-performance energy-efficient GPU memory design.” Acm Journal on Emerging Technologies in Computing Systems 15, no. 4 (December 1, 2019). https://doi.org/10.1145/3330152.
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    • Yang, J., X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. “Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 38, no. 1 (January 1, 2019): 57–69. https://doi.org/10.1109/TCAD.2018.2802870.
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    • Wang, D., L. Ma, M. Zhang, J. An, H. H. Li, and Y. Chen. “Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.” Journal of Circuits, Systems and Computers 27, no. 5 (May 1, 2018). https://doi.org/10.1142/S0218126618500810.
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    • Zhang, L., W. Song, J. J. Yang, H. Li, and Y. Chen. “A compact model for selectors based on metal doped electrolyte.” Applied Physics A: Materials Science and Processing 124, no. 4 (April 1, 2018). https://doi.org/10.1007/s00339-018-1706-2.
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    • Basu, A., J. Acharya, T. Karnik, H. Liu, H. Li, J. S. Seo, and C. Song. “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 1 (March 1, 2018): 6–27. https://doi.org/10.1109/JETCAS.2018.2816339.
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    • Chen, Y., H. Li, C. Wu, C. Song, S. Li, C. Min, H. P. Cheng, W. Wen, and X. Liu. “Neuromorphic computing's yesterday, today, and tomorrow – an evolutional view.” Integration 61 (March 1, 2018): 49–61. https://doi.org/10.1016/j.vlsi.2017.11.001.
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    • Mohanty, S. P., M. Hüebner, C. J. Xue, X. Li, and H. Li. “Guest editorial circuit and system design automation for internet of things.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 1 (January 1, 2018): 3–6. https://doi.org/10.1109/TCAD.2017.2779960.
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    • Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.” Ieee Transactions on Computers 66, no. 9 (September 1, 2017): 1478–90. https://doi.org/10.1109/TC.2017.2690855.
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    • Hu, M., Y. Chen, J. J. Yang, Y. Wang, and H. Li. “A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (August 1, 2017): 1353–66. https://doi.org/10.1109/TCAD.2016.2618866.
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    • Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1167–80. https://doi.org/10.1109/TCAD.2016.2619480.
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    • Bi, X., M. Mao, D. Wang, and H. Li. “Cross-layer optimization for multilevel cell STT-RAM caches.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (June 1, 2017): 1807–20. https://doi.org/10.1109/TVLSI.2017.2665543.
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    • Chen, Y., H. H. Li, I. Bayram, and E. Eken. “Recent Technology Advances of Emerging Memories.” Ieee Design and Test 34, no. 3 (June 1, 2017): 8–22. https://doi.org/10.1109/MDAT.2017.2685381.
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    • Eken, E., I. Bayram, Y. Zhang, B. Yan, H. Li, and Y. Chen. “Giant Spin-Hall assisted STT-RAM and logic design.” Integration, the Vlsi Journal 58 (June 1, 2017): 253–61. https://doi.org/10.1016/j.vlsi.2017.04.002.
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    • Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” Ieee Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.
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    • Li, H. H., Y. Chen, C. Liu, J. P. Strachan, and N. Davila. “Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.” Ieee Consumer Electronics Magazine 6, no. 1 (January 1, 2017): 94–103. https://doi.org/10.1109/MCE.2016.2614523.
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    • Wu, Chunpeng, Hsin‐Pai Cheng, Sicheng Li, Hai Helen Li, and Yiran Chen. “ApesNet: a pixel‐wise efficient segmentation network for embedded devices.” Iet Cyber Physical Systems: Theory & Applications 1, no. 1 (December 2016): 78–85. https://doi.org/10.1049/iet-cps.2016.0027.
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    • Li, H. H., Q. Qiu, and Y. Wang. “Guest Editorial: Design and Applications of Neuromorphic Computing System.” Ieee Transactions on Multi Scale Computing Systems 2, no. 4 (October 1, 2016): 223–24. https://doi.org/10.1109/TMSCS.2016.2631918.
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    • Qiu, Q., Z. Li, K. Ahmed, W. Liu, S. F. Habib, H. Li, and M. Hu. “A Neuromorphic Architecture for Context Aware Text Image Recognition.” Journal of Signal Processing Systems 84, no. 3 (September 1, 2016): 355–69. https://doi.org/10.1007/s11265-015-1067-4.
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    • Pyle, S. D., H. Li, and R. F. DeMara. “Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device.” Electronics Letters 52, no. 14 (July 7, 2016): 1238–40. https://doi.org/10.1049/el.2015.4114.
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    • Hu, M., Y. Wang, W. Wen, and H. Li. “Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 235–46. https://doi.org/10.1109/JETCAS.2016.2547780.
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    • Yang, J., Z. Sun, X. Wang, Y. Chen, and H. Li. “Spintronic Memristor as Interface between DNA and Solid State Devices.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 212–21. https://doi.org/10.1109/JETCAS.2016.2547700.
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    • Duan, S., Z. Dong, X. Hu, L. Wang, and H. Li. “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.” Neural Computing and Applications 27, no. 4 (May 1, 2016): 837–44. https://doi.org/10.1007/s00521-015-1899-7.
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    • Liu, X., M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, et al. “Harmonica: A Framework of Heterogeneous Computing Systems with Memristor-Based Neuromorphic Computing Accelerators.” Ieee Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 1, 2016): 617–28. https://doi.org/10.1109/TCSI.2016.2529279.
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    • Mao, F., Y. C. Chen, W. Zhang, H. Li, and B. He. “Library-based placement and routing in FPGAs with support of partial reconfiguration.” Acm Transactions on Design Automation of Electronic Systems 21, no. 4 (May 1, 2016). https://doi.org/10.1145/2901295.
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    • Sun, Z., X. Bi, W. Wu, S. Yoo, and H. H. Li. “Array Organization and Data Management Exploration in Racetrack Memory.” Ieee Transactions on Computers 65, no. 4 (April 1, 2016): 1041–54. https://doi.org/10.1109/TC.2014.2360545.
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    • Yang, J., P. Wang, Y. Zhang, Y. Cheng, W. Zhao, Y. Chen, and H. H. Li. “Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 3 (March 1, 2016): 380–93. https://doi.org/10.1109/TCAD.2015.2474366.
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    • Zhang, Y., Y. Li, Z. Sun, H. Li, Y. Chen, and A. K. Jones. “Read performance: The newest barrier in scaled stt-ram.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 23, no. 6 (June 1, 2015): 1170–74. https://doi.org/10.1109/TVLSI.2014.2326797.
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    • Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A novel self-reference technique for STT-RAM read and write reliability enhancement.” Ieee Transactions on Magnetics 50, no. 11 (November 1, 2014). https://doi.org/10.1109/TMAG.2014.2323196.
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    • Hu, Miao, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, and Richard W. Linderman. “Memristor crossbar-based neuromorphic computing system: a case study.” Ieee Transactions on Neural Networks and Learning Systems 25, no. 10 (October 2014): 1864–78. https://doi.org/10.1109/tnnls.2013.2296777.
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    • Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” Thescientificworldjournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.
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    • Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.
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    • Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” Acm Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.
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    • Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.” Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013). https://doi.org/10.1145/2500459.
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    • Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache.” Acm Transactions on Architecture and Code Optimization 10, no. 4 (January 1, 2013): 1–22. https://doi.org/10.1145/2541228.2555308.
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    • Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” Ieee Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.
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    • Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” Ieee Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.
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    • Li, H. H., and Z. Sun. “Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400085.
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    • Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” Acm Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.
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    • Sun, Z., H. Li, and X. Wang. “Magnetic tunnel junction design margin exploration for self-reference sensing scheme.” Journal of Applied Physics 111, no. 7 (April 2012): 7C726–7263. https://doi.org/10.1063/1.3679647.
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    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme.” Ieee Journal of Solid State Circuits 47, no. 2 (February 1, 2012): 560–73. https://doi.org/10.1109/JSSC.2011.2170778.
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    • Sun, Z., H. Li, Y. Chen, and X. Wang. “Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (January 1, 2012): 2020–30. https://doi.org/10.1109/TVLSI.2011.2166282.
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    • Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity.” Neural Plasticity 2012 (January 2012): 272374. https://doi.org/10.1155/2012/272374.
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    • Li, H., X. Wang, Z. L. Ong, W. F. Wong, Y. Zhang, P. Wang, and Y. Chen. “Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2356–59. https://doi.org/10.1109/TMAG.2011.2159262.
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    • Wang, P., X. Wang, Y. Zhang, H. Li, S. P. Levitan, and Y. Chen. “Nonpersistent errors optimization in spin-MOS logic and storage circuitry.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 3860–63. https://doi.org/10.1109/TMAG.2011.2153838.
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    • Zhang, Y., X. Wang, H. Li, and Y. Chen. “STT-RAM cell optimization considering MTJ and CMOS variations.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2962–65. https://doi.org/10.1109/TMAG.2011.2158810.
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    • Dong, X., X. Wu, Y. Xie, Y. Chen, and H. Li. “Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation.” Iet Computers and Digital Techniques 5, no. 3 (May 1, 2011): 213–20. https://doi.org/10.1049/iet-cdt.2009.0091.
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    • Hu, M., H. H. Li, Y. Chen, and X. Wang. “Spintronic memristor: Compact model and statistical analysis.” Journal of Low Power Electronics 7, no. 2 (April 1, 2011): 234–44. https://doi.org/10.1166/jolpe.2011.1131.
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    • Zhu, W., H. Li, Y. Chen, and X. Wang. “Current switching in MgO-based magnetic tunneling junctions.” Ieee Transactions on Magnetics 47, no. 1 PART 2 (January 1, 2011): 156–60. https://doi.org/10.1109/TMAG.2010.2085441.
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    • Chen, Y., X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. “Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (December 1, 2010): 1724–34. https://doi.org/10.1109/TVLSI.2009.2032192.
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    • Chen, Y., W. Tian, H. Li, X. Wang, and W. Zhu. “PCMO device with high switching stability.” Ieee Electron Device Letters 31, no. 8 (August 1, 2010): 866–68. https://doi.org/10.1109/LED.2010.2050457.
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    • Chen, Y., and H. Li. “Patents relevant to cross-point memory array.” Recent Patents on Electrical Engineering 3, no. 2 (June 25, 2010): 114–24. https://doi.org/10.2174/1874476111003020114.
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    • Xi, H., J. Stricklin, H. Li, Y. Chen, X. Wang, Y. Zheng, Z. Gao, and M. X. Tang. “Spin transfer torque memory with thermal assist mechanism: A case study.” Ieee Transactions on Magnetics 46, no. 3 PART 2 (March 1, 2010): 860–65. https://doi.org/10.1109/TMAG.2009.2033674.
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    • Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.
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    • Wang, X., Y. Chen, Y. Gu, and H. Li. “Spintronic memristor temperature sensor.” Ieee Electron Device Letters 31, no. 1 (January 1, 2010): 20–22. https://doi.org/10.1109/LED.2009.2035643.
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    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.
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    • Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.
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    • Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” Ieee Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.
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    • Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” Ieee Transactions on Magnetics 44, no. 11 PART 2 (November 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.
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    • Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.
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    • Li, H., S. Bhunia, Y. Chen, K. Roy, and T. N. Vijaykumar. “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (March 1, 2004): 245–54. https://doi.org/10.1109/TVLSI.2004.824307.
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    • Agarwal, A., H. Li, and K. Roy. “A single-Vt low-leakage gated-ground cache for deep submicron.” Ieee Journal of Solid State Circuits 38, no. 2 (February 1, 2003): 319–28. https://doi.org/10.1109/JSSC.2002.807414.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, M. Albrecht, A. Amoroso, F. F. An, Q. An, et al. “Measurement of e+e−→π0π0ψ(3686) at s from 4.009 to 4.600 GeV and observation of a neutral charmoniumlike structure.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.052001.
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    • Ablikim, M., M. N. Achasov, S. Ahmed, O. Albayrak, M. Albrecht, M. Alekseev, D. J. Ambrose, et al. “Study of η(1475) and X(1835) in radiative J/ψ decays to γϕ.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.051101.
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  • Book Sections

    • Li, Z., C. Liu, H. Li, and Y. Chen. “Neuromorphic hardware acceleration enabled by emerging technologies.” In Emerging Technology and Architecture for Big-Data Analytics, 217–44, 2017. https://doi.org/10.1007/978-3-319-54840-1_10.
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    • Chen, Y. C., Y. Wang, W. Zhang, Y. Chen, and H. H. Li. “In-place logic obfuscation for emerging nonvolatile FPGAs.” In Fundamentals of IP and SoC Security: Design, Verification, and Debug, 277–93, 2017. https://doi.org/10.1007/978-3-319-50057-7_11.
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    • Yang, C., H. Li, and Y. Chen. “Nanoscale memory architectures for neuromorphic computing.” In Security Opportunities in Nano Devices and Emerging Technologies, 215–34, 2017. https://doi.org/10.1201/9781315265056.
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    • Zhang, Y., W. Wen, H. Li, and Y. Chen. “The prospect of STT-RAM scaling.” In Metallic Spintronic Devices, 71–103, 2017. https://doi.org/10.1201/b17238.
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    • Li, H. H., M. Hu, and B. Liu. “Memristor modeling - static, statistical, and stochastic methodologies.” In Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, 313–35, 2016. https://doi.org/10.1049/PBCS029E_ch11.
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    • Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.
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    • Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.
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    • Chen, Y., H. Li, Y. Xie, and D. Niu. “Low Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing. CRC Press, 2012.
    • Li, H. H., M. Hu, and R. E. Pino. “Statistical memristor model and its applications in neuromorphic computing.” In Advances in Neuromorphic Memristor Science and Applications, 107–31, 2012. https://doi.org/10.1007/978-94-007-4491-2_8.
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    • Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.

  • Conference Papers

    • Zhang, S., H. H. Li, and U. Schlichtmann. “Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 107–13, 2021. https://doi.org/10.1145/3394885.3431523.
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    • Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.” In Proceedings  2020 Ieee International Conference on Artificial Intelligence Circuits and Systems, Aicas 2020, 11–15, 2020. https://doi.org/10.1109/AICAS48895.2020.9073995.
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    • Kim, B., and H. Li. “Leveraging 3D vertical RRAM to developing neuromorphic architecture for pattern classification.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2020-July:258–63, 2020. https://doi.org/10.1109/ISVLSI49217.2020.00054.
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    • Li, Z., B. Yan, and H. H. Li. “ReSiPE: ReRAM-based single-spiking processing-in-memory engine.” In Proceedings  Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218578.
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    • Zheng, Q., Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. L. Yang, and H. H. Li. “Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks.” In Proceedings  Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218590.
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    • Zhang, J., J. Huang, M. Deisher, H. Li, and Y. Chen. “Structural sparsification for far-field speaker recognition with intel R GNA.” In Icassp, Ieee International Conference on Acoustics, Speech and Signal Processing  Proceedings, 2020-May:3037–41, 2020. https://doi.org/10.1109/ICASSP40776.2020.9054569.
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    • Joardar, B. K., N. Kannappan Jayakodi, J. R. Doppa, H. Li, P. P. Pande, and K. Chakrabarty. “GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 228–33, 2020. https://doi.org/10.23919/DATE48585.2020.9116273.
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    • Wang, Y., F. Chen, L. Song, C. J. Richard Shi, H. H. Li, and Y. Chen. “ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1472–77, 2020. https://doi.org/10.23919/DATE48585.2020.9116422.
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    • Zhang, S., B. Li, H. H. Li, and U. Schlichtmann. “A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1426–31, 2020. https://doi.org/10.23919/DATE48585.2020.9116323.
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    • Chen, F., L. Song, H. H. Li, and Y. Chen. “PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2020-January:175–80, 2020. https://doi.org/10.1109/ASP-DAC47756.2020.9045555.
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    • Song, L., F. Chen, Y. Chen, and H. H. Li. “Parallelism in Deep Learning Accelerators.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2020-January:645–50, 2020. https://doi.org/10.1109/ASP-DAC47756.2020.9045206.
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    • Chen, F., W. Wen, L. Song, J. Zhang, H. H. Li, and Y. Chen. “How to obtain and run light and efficient deep learning networks.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, Vol. 2019-November, 2019. https://doi.org/10.1109/ICCAD45719.2019.8942106.
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    • Yang, Q., J. Mao, Z. Wang, and H. Li. “DASNet: Dynamic activation sparsity for neural network efficiency improvement.” In Proceedings  International Conference on Tools With Artificial Intelligence, Ictai, 2019-November:1401–5, 2019. https://doi.org/10.1109/ICTAI.2019.00197.
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    • Joardar, B. K., B. Li, J. R. Doppa, H. Li, P. P. Pande, and K. Chakrabarty. “REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.” In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, Date 2019, 522–27, 2019. https://doi.org/10.23919/DATE.2019.8714802.
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    • Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.” In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, Date 2019, 1751–56, 2019. https://doi.org/10.23919/DATE.2019.8714954.
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    • Li, B., B. Yan, and H. Li. “An overview of in-memory processing with emerging non-volatile memory for data-intensive applications.” In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 381–86, 2019. https://doi.org/10.1145/3299874.3319452.
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    • Zhang, J., W. Wen, M. Deisher, H. P. Cheng, H. Li, and Y. Chen. “Learning Efficient Sparse Structures in Speech Recognition.” In Icassp, Ieee International Conference on Acoustics, Speech and Signal Processing  Proceedings, 2019-May:2717–21, 2019. https://doi.org/10.1109/ICASSP.2019.8683620.
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    • Guo, X., Y. Huang, H. P. Cheng, B. Li, W. Wen, S. Ma, H. Li, and Y. Chen. “Exploration of Automatic Mixed-Precision Search for Deep Neural Networks.” In Proceedings 2019 Ieee International Conference on Artificial Intelligence Circuits and Systems, Aicas 2019, 276–78, 2019. https://doi.org/10.1109/AICAS.2019.8771498.
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    • Cheng, H. P., Q. Wu, J. Shen, H. Li, H. Yang, and Y. Chen. “AdverQuil: An efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 557–62, 2019. https://doi.org/10.1145/3287624.3288753.
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    • Li, B., C. Liu, B. Yan, and H. Li. “Build reliable and efficient neuromorphic design with memristor technology.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 224–29, 2019. https://doi.org/10.1145/3287624.3288744.
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    • Min, C., J. Mao, H. Li, and Y. Chen. “NeuralHMC: An efficient HMC-based accelerator for deep neural networks.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 432–37, 2019. https://doi.org/10.1145/3287624.3287642.
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    • Nixon, K. W., J. Mao, J. Shen, H. Yang, H. H. Li, and Y. Chen. “SPN dash: Fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2018. https://doi.org/10.1145/3240765.3240851.
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    • Li, H. H., Y. Wang, and W. Wen. “Message from the technical program chairs.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:xiii–xiv, 2018. https://doi.org/10.1109/ISVLSI.2018.00006.
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    • Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, Y. Chen, and H. Li. “MAT: A multi-strength adversarial training method to mitigate adversarial attacks.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:476–81, 2018. https://doi.org/10.1109/ISVLSI.2018.00092.
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    • Jiang, H., K. Yamada, Z. Ren, T. Kwok, F. Luo, Q. Yang, X. Zhang, et al. “Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351276.
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    • Li, B., F. Chen, W. Kang, W. Zhao, Y. Chen, and H. Li. “Design and Data Management for Magnetic Racetrack Memory.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351681.
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    • Yang, Q., H. Li, and Q. Wu. “A Quantized Training Method to Enhance Accuracy of ReRAM-based Neuromorphic Systems.” In Proceedings  Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351327.
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    • Ji, H., L. Song, L. Jiang, H. H. Li, and Y. Chen. “Recom: An efficient resistive accelerator for compressed deep neural networks.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:237–40, 2018. https://doi.org/10.23919/DATE.2018.8342009.
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    • Li, B., L. Song, F. Chen, X. Qian, Y. Chen, and H. Li. “ReRAM-based accelerator for deep learning.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:815–20, 2018. https://doi.org/10.23919/DATE.2018.8342118.
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    • Yan, B., F. Chen, Y. Zhang, C. Song, H. Li, and Y. Chen. “Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.” In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, Date 2018, 2018-January:109–12, 2018. https://doi.org/10.23919/DATE.2018.8341988.
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    • Song, L., Y. Zhuo, X. Qian, H. Li, and Y. Chen. “GraphR: Accelerating Graph Processing Using ReRAM.” In Proceedings  International Symposium on High Performance Computer Architecture, 2018-February:531–43, 2018. https://doi.org/10.1109/HPCA.2018.00052.
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    • Wang, P., S. Li, G. Sun, X. Wang, Y. Chen, H. Li, J. Cong, N. Xiao, and T. Zhang. “RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.” In Proceedings  International Symposium on High Performance Computer Architecture, 2018-February:518–30, 2018. https://doi.org/10.1109/HPCA.2018.00051.
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    • Chen, F., Z. Li, W. Kang, W. Zhao, H. Li, and Y. Chen. “Process variation aware data management for magnetic skyrmions racetrack memory.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:221–26, 2018. https://doi.org/10.1109/ASPDAC.2018.8297309.
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    • Eken, E., I. Bayram, H. H. Li, and Y. Chen. “Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:375–80, 2018. https://doi.org/10.1109/ASPDAC.2018.8297352.
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    • Jia, X., J. Yang, Z. Wang, Y. Chen, H. H. Li, and W. Zhao. “Spintronics based stochastic computing for efficient Bayesian inference system.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:580–85, 2018. https://doi.org/10.1109/ASPDAC.2018.8297385.
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    • Li, B., W. Wen, J. Mao, S. Li, Y. Chen, and H. H. Li. “Running sparse and low-precision neural network: When algorithm meets hardware.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:534–39, 2018. https://doi.org/10.1109/ASPDAC.2018.8297378.
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    • Liu, X., W. Wen, X. Qian, H. Li, and Y. Chen. “Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2018-January:141–46, 2018. https://doi.org/10.1109/ASPDAC.2018.8297296.
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    • Yan, B., C. Liu, X. Liu, Y. Chen, and H. Li. “Understanding the trade-offs of device, circuit and application in ReRAM-based neuromorphic computing systems.” In Technical Digest  International Electron Devices Meeting, Iedm, 11.4.1-11.4.4, 2018. https://doi.org/10.1109/IEDM.2017.8268371.
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    • Liu, C., F. Liu, and H. Li. “Beyond CMOS: Memristor and its application for next generation storage and computing.” In Ecs Transactions, 85:115–25, 2018. https://doi.org/10.1149/08506.0115ecst.
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    • Wen, W., C. Xu, C. Wu, Y. Wang, Y. Chen, and H. Li. “Coordinating Filters for Faster Deep Neural Networks.” In Proceedings of the Ieee International Conference on Computer Vision, 2017-October:658–66, 2017. https://doi.org/10.1109/ICCV.2017.78.
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    • Broyde, L., K. Nixon, X. Chen, H. Li, and Y. Chen. “MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices.” In International System on Chip Conference, 2017-September:221–26, 2017. https://doi.org/10.1109/SOCC.2017.8226044.
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    • Mao, J., Z. Qin, Z. Xu, K. W. Nixon, X. Chen, H. Li, and Y. Chen. “AdaLearner: An adaptive distributed mobile learning system for neural networks.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:291–96, 2017. https://doi.org/10.1109/ICCAD.2017.8203791.
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    • Mao, J., Z. Yang, W. Wen, C. Wu, L. Song, K. W. Nixon, X. Chen, H. Li, and Y. Chen. “MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:751–56, 2017. https://doi.org/10.1109/ICCAD.2017.8203852.
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    • Yan, B., J. Yang, Q. Wu, Y. Chen, and H. Li. “A closed-loop design to enhance weight stability of memristor based neural network chips.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 2017-November:541–48, 2017. https://doi.org/10.1109/ICCAD.2017.8203824.
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    • Wu, C., W. Wen, T. Afzal, Y. Zhang, Y. Chen, and H. H. Li. “A compact DNN: Approaching GoogLeNet-level accuracy of classification and domain adaptation.” In Proceedings  30th Ieee Conference on Computer Vision and Pattern Recognition, Cvpr 2017, 2017-January:761–70, 2017. https://doi.org/10.1109/CVPR.2017.88.
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    • Song, C., B. Liu, W. Wen, H. Li, and Y. Chen. “A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.” In Nvmsa 2017  6th Ieee Non Volatile Memory Systems and Applications Symposium, 2017. https://doi.org/10.1109/NVMSA.2017.8064465.
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    • Liu, C., F. Liu, and H. Li. “Brain-inspired computing accelerated by memristor technology.” In Proceedings of the 4th Acm International Conference on Nanoscale Computing and Communication, Nanocom 2017, 2017. https://doi.org/10.1145/3109453.3123960.
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    • Hassan, A. M., H. H. Li, and Y. Chen. “Hardware implementation of echo state networks using memristor double crossbar arrays.” In Proceedings of the International Joint Conference on Neural Networks, 2017-May:2171–77, 2017. https://doi.org/10.1109/IJCNN.2017.7966118.
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    • Li, S., W. Wen, Y. Wang, S. Han, Y. Chen, and H. H. Li. “An FPGA design framework for CNN sparsification and acceleration.” In Proceedings  Ieee 25th Annual International Symposium on Field Programmable Custom Computing Machines, Fccm 2017, 28, 2017. https://doi.org/10.1109/FCCM.2017.21.
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    • Niu, D., R. Xue, T. Cai, H. Li, K. Effah, and H. Zhang. “The new large-scale RNNLM system based on distributed neuron.” In Proceedings  2017 Ieee 31st International Parallel and Distributed Processing Symposium Workshops, Ipdpsw 2017, 433–36, 2017. https://doi.org/10.1109/IPDPSW.2017.21.
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    • Liu, C., M. Hu, J. P. Strachan, and H. H. Li. “Rescuing Memristor-based Neuromorphic Design with High Defects.” In Proceedings  Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062310.
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    • Wang, Y., W. Wen, B. Liu, D. Chiarulli, and H. H. Li. “Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks.” In Proceedings  Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062256.
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    • Cheng, H. P., W. Wen, C. Wu, S. Li, H. Li, and Y. Chen. “Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.” In Proceedings of the 2017 Design, Automation and Test in Europe, Date 2017, 139–44, 2017. https://doi.org/10.23919/DATE.2017.7926972.
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    • Hassan, A. M., C. Yang, C. Liu, H. Li, and Y. Chen. “Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.” In Proceedings of the 2017 Design, Automation and Test in Europe, Date 2017, 776–81, 2017. https://doi.org/10.23919/DATE.2017.7927094.
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    • Song, L., X. Qian, H. Li, and Y. Chen. “PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.” In Proceedings  International Symposium on High Performance Computer Architecture, 541–52, 2017. https://doi.org/10.1109/HPCA.2017.55.
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    • Cline, B. T., S. Heinrich-Barna, P. J. Wright, H. Li, V. Viswanath, S. Hu, P. Wesling, G. Qu, S. Ghosh, and A. A. Iranmanesh. “Welcome.” In Proceedings  International Symposium on Quality Electronic Design, Isqed, 2017. https://doi.org/10.1109/ISQED.2017.7918277.
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    • Liu, C., Q. Yang, C. Zhang, H. Jiang, Q. Wu, and H. Li. “A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 647–52, 2017. https://doi.org/10.1109/ASPDAC.2017.7858397.
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    • Min, C., J. Guo, H. Li, and Y. Chen. “Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 764–69, 2017. https://doi.org/10.1109/ASPDAC.2017.7858416.
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    • Wang, Y., W. Wen, L. Song, and H. Li. “Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 776–81, 2017. https://doi.org/10.1109/ASPDAC.2017.7858418.
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    • Li, H. H., P. Ghosal, and T. Theocharides. “Message from the Technical Program Chairs.” In Proceedings  2016 Ieee International Symposium on Nanoelectronic and Information Systems, Inis 2016, xiii–xiv, 2017. https://doi.org/10.1109/iNIS.2016.007.
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    • Li, Hai. “Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies.” In 2017 International Symposium on Vlsi Design, Automation and Test (Vlsi Dat). IEEE, 2017.
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    • Wen, W., C. Xu, F. Yan, C. Wu, Y. Wang, Y. Chen, and H. Li. “TernGrad: Ternary gradients to reduce communication in distributed deep learning.” In Advances in Neural Information Processing Systems, 2017-December:1510–20, 2017.
    • Yan, B., Z. Li, Y. Chen, and H. Li. “RAM and TCAM designs by using STT-MRAM.” In 2016 16th Non Volatile Memory Technology Symposium, Nvmts 2016, 18–22, 2016. https://doi.org/10.1109/NVMTS.2016.7781514.
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    • Song, C., B. Liu, C. Liu, H. Li, and Y. Chen. “Design techniques of eNVM-enabled neuromorphic computing systems.” In Proceedings of the 34th Ieee International Conference on Computer Design, Iccd 2016, 674–77, 2016. https://doi.org/10.1109/ICCD.2016.7753356.
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    • Liu, C., Y. Chen, and H. Li. “Neural processor design enabled by memristor technology.” In 2016 Ieee International Conference on Rebooting Computing, Icrc 2016  Conference Proceedings, 2016. https://doi.org/10.1109/ICRC.2016.7738693.
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    • Bi, X., H. Li, and J. J. Kim. “Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design.” In Proceedings  2012 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2012, 374–79, 2012. https://doi.org/10.1109/ISVLSI.2012.56.
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    • Chen, Y. C., H. Li, and W. Zhang. “A novel peripheral circuit for RRAM-based LUT.” In Iscas 2012  2012 Ieee International Symposium on Circuits and Systems, 1811–14, 2012. https://doi.org/10.1109/ISCAS.2012.6271619.
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    • Sun, Z., H. Li, and W. Wu. “A dual-mode architecture for fast-switching STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 45–50, 2012. https://doi.org/10.1145/2333660.2333673.
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    • Sun, Z., X. Bi, and H. Li. “Process variation aware data management for STT-RAM cache design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 179–84, 2012. https://doi.org/10.1145/2333660.2333706.
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    • Hu, M., H. Li, Q. Wu, G. S. Rose, and Y. Chen. “Memristor crossbar based hardware realization of BSB recall function.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252563.
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    • Wang, H., H. Li, and R. E. Pino. “Memristor-based synapse design and training scheme for neuromorphic computing architecture.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252577.
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    • Hu, M., H. Li, Q. Wu, and G. S. Rose. “Hardware realization of BSB recall function using memristor crossbar arrays.” In Proceedings  Design Automation Conference, 498–503, 2012. https://doi.org/10.1145/2228360.2228448.
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    • Pino, R. E., H. Li, Y. Chen, M. Hu, and B. Liu. “Statistical memristor modeling and case study in neuromorphic computing.” In Proceedings  Design Automation Conference, 585–90, 2012. https://doi.org/10.1145/2228360.2228466.
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    • Bi, X., C. Zhang, H. Li, Y. Chen, and R. E. Pino. “Spintronic memristor based temperature sensor design with CMOS current reference.” In Proceedings  Design, Automation and Test in Europe, Date, 1301–6, 2012.
    • Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Architecting a common-source-line array for bipolar non-volatile memory devices.” In Proceedings  Design, Automation and Test in Europe, Date, 1451–54, 2012.
    • Chen, X., J. Zeng, Y. Chen, W. Zhang, and H. Li. “Fine-grained dynamic voltage scaling on OLED display.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 807–12, 2012. https://doi.org/10.1109/ASPDAC.2012.6165066.
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    • Chen, Y. C., W. Zhang, and H. Li. “A look up table design with 3D bipolar RRAMs.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 73–78, 2012. https://doi.org/10.1109/ASPDAC.2012.6165051.
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    • Bi, X., Z. Sun, H. Li, and W. Wu. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 88–94, 2012. https://doi.org/10.1145/2429384.2429401.
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    • Hu, M., H. Li, and R. E. Pino. “Fast statistical model of TiO 2 thin-film memristor and design implication.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 345–52, 2011. https://doi.org/10.1109/ICCAD.2011.6105353.
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    • Joshi, R., R. Kanj, P. Wang, and H. H. Li. “Universal statistical cure for predicting memory loss.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 236–39, 2011. https://doi.org/10.1109/ICCAD.2011.6105333.
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    • Sun, Z., X. Bi, H. Li, W. F. Wong, Z. L. Ong, X. Zhu, and W. Wu. “Multi retention level STT-RAM cache designs with a dynamic refresh scheme.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 329–38, 2011. https://doi.org/10.1145/2155620.2155659.
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    • Xue, C. J., Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li. “Emerging non-volatile memories: Opportunities and challenges.” In Embedded Systems Week 2011, Esweek 2011  Proceedings of the 9th Ieee/Acm/Ifip International Conference on Hardware/Software Codesign and System Synthesis, Codes+Isss’11, 325–34, 2011. https://doi.org/10.1145/2039370.2039420.
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    • Wang, P., X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu. “A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.” In Proceedings of the Custom Integrated Circuits Conference, 2011. https://doi.org/10.1109/CICC.2011.6055392.
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    • Chen, Y., W. F. Wong, H. Li, and C. K. Koh. “Processor caches built using multi-level spin-transfer torque RAM cells.” In Proceedings of the International Symposium on Low Power Electronics and Design, 73–78, 2011. https://doi.org/10.1109/ISLPED.2011.5993610.
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    • Chen, Y. C., H. Li, W. Zhang, and R. E. Pino. “3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design.” In Proceedings of the 2011 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2011, 59–64, 2011. https://doi.org/10.1109/NANOARCH.2011.5941484.
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    • Chen, Y. C., H. Li, Y. Chen, and R. E. Pino. “3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.” In Proceedings  Design, Automation and Test in Europe, Date, 583–86, 2011.
    • Chen, Y., and H. Li. “Emerging sensing techniques for emerging memories.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 204–10, 2011. https://doi.org/10.1109/ASPDAC.2011.5722185.
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    • Joshi, Rajiv, Rouwaida Kanj, Peiyuan Wang, and Hai Helen Li. “Universal Statistical Cure For Predicting Memory Loss (Invited Paper).” In 2011 Ieee/Acm International Conference on Computer Aided Design (Iccad), 236–39. IEEE, 2011.
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    • Chen, Y., H. Li, X. Wang, and J. Park. “Applications of TMR devices in solid state circuits and systems.” In 2010 International Soc Design Conference, Isocc 2010, 252–55, 2010. https://doi.org/10.1109/SOCDC.2010.5682923.
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    • Sun, Z., H. Li, Y. Chen, and X. Wang. “Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement.” In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 432–37, 2010. https://doi.org/10.1109/ICCAD.2010.5653720.
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    • Chen, Y., H. Li, and X. Wang. “Spintronic devices: From memory to memristor.” In 2010 International Conference on Communications, Circuits and Systems, Icccas 2010  Proceedings, 811–16, 2010. https://doi.org/10.1109/ICCCAS.2010.5581868.
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    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 1–6, 2010. https://doi.org/10.1145/1840845.1840847.
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    • Chen, Y., X. Wang, W. Zhu, H. Li, Z. Sun, G. Sun, and Y. Xie. “Access scheme of multi-level cell spin-transfer torque random access memory and its optimization.” In Midwest Symposium on Circuits and Systems, 1109–12, 2010. https://doi.org/10.1109/MWSCAS.2010.5548848.
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    • Chen, Y., X. Wang, Z. Sun, and H. Li. “The application of spintronic devices in magnetic bio-sensing.” In Proceedings of the 2nd Asia Symposium on Quality Electronic Design, Asqed 2010, 230–34, 2010. https://doi.org/10.1109/ASQED.2010.5548244.
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    • Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM).” In Proceedings  Design, Automation and Test in Europe, Date, 148–53, 2010.
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    • Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.” In Proceedings  Ieee International Conference on Computer Design: Vlsi in Computers and Processors, 268–74, 2009. https://doi.org/10.1109/ICCD.2009.5413145.
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    • Li, H., H. Xi, Y. Chen, J. Stricklin, X. Wang, and T. Zhang. “Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration.” In Proceedings of the 2009 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2009, 217–22, 2009. https://doi.org/10.1109/ISVLSI.2009.17.
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    • Dong, X., X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.” In Proceedings  Design Automation Conference, 554–59, 2008. https://doi.org/10.1109/DAC.2008.4555878.
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    • Chen, Y., X. Wang, H. Li, H. Liu, and D. V. Dimitrov. “Design margin exploration of Spin-Torque Transfer RAM (SPRAM).” In Proceedings of the 9th International Symposium on Quality Electronic Design, Isqed 2008, 684–90, 2008. https://doi.org/10.1109/ISQED.2008.4479820.
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    • Chen, Yiran, Xiaobin Wang, Hai Li, Harry Liu, and Dimitar V. Dimitrov. “Design margin exploration of spin-torque transfer RAM (SPRAM).” In Isqed 2008: Proceedings of the Ninth International Symposium on Quality Electronic Design, 684–90. IEEE COMPUTER SOC, 2008. https://doi.org/10.1109/ISQED.2008.140.
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    • Chen, Y., H. Li, J. Li, and C. K. Koh. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” In Proceedings of the International Symposium on Low Power Electronics and Design, 195–200, 2007. https://doi.org/10.1145/1283780.1283822.
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    • Wong, W. F., C. K. Kon, Y. Chen, and H. Li. “VOSCH: Voltage scaled cache hierarchies.” In 2007 Ieee International Conference on Computer Design, Iccd 2007, 496–503, 2007. https://doi.org/10.1109/ICCD.2007.4601944.
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    • Li, H., Y. Chen, K. Roy, and C. K. Koh. “SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design.” In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 2006:158–63, 2006.
    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Cascaded carry-select adder (C² SA): A new structure for low-power CSA design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 115–18, 2005.
    • Chen, Y. R., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Cicc: Proceedings of the Ieee 2005 Custom Integrated Circuits Conference, 775–78. IEEE, 2005.
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    • Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Proceedings of the Custom Integrated Circuits Conference, 2005:775–78, 2005. https://doi.org/10.1109/CICC.2005.1568783.
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    • Li, H., C. Y. Cher, T. N. Vijaykumar, and K. Roy. “VSV: L2-miss-driven variable supply-voltage scaling for low power.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 2003-January:19–28, 2003. https://doi.org/10.1109/MICRO.2003.1253180.
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    • Li, H., S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy. “Deterministic clock gating for microprocessor power reduction.” In Proceedings  International Symposium on High Performance Computer Architecture, 12:113–22, 2003. https://doi.org/10.1109/HPCA.2003.1183529.
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    • Agarwal, A., H. Li, and K. Roy. “DRG-Cache: A data retention gated-ground cache for low power.” In Proceedings  Design Automation Conference, 473–78, 2002. https://doi.org/10.1109/dac.2002.1012671.
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    • Bhunia, S., H. Li, and K. Roy. “A high performance IDDQ testable cache for scaled CMOS technologies.” In Proceedings of the Asian Test Symposium, 2002-January:157–62, 2002. https://doi.org/10.1109/ATS.2002.1181704.
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    • Chen, Ying, Peng Liu, and Zhi Wu Yu. “Research on the Sol-Gel Method of Preparing Ternary Nano SiO₂-Al₂O₃-TiO₂ Materials.” In Key Engineering Materials, 609–610:281–87. Trans Tech Publications, Ltd., n.d. https://doi.org/10.4028/www.scientific.net/kem.609-610.281.
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