Hai "Helen" Li | Scholars@Duke

Hai "Helen" Li
Associate Professor in the Department of Electrical and Computer Engineering

Research Interests:
Brain-inspired computing systems and neuromorphic design, memory design and architecture based on conventional and emerging technologies, and device/circuit/architecture co-design for low power and high performance.

Current Research Interests

Brain-inspired computing systems and neuromorphic design, memory design and architecture based on conventional and emerging technologies, and device/circuit/architecture co-design for low power and high performance.

Office Hours

Appointment by email hai.li@duke.edu

Current Appointments & Affiliations

Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2017
Associate Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2018

Contact Information

Rm103 Hudson Hall, 100 Science Dr., Durham, NC 27701
Rm130 Hudson Hall, Box 90291, Durham, NC 27701
hai.li@duke.edu (919) 660-1373
Google Scholar
Personal page

Background
Education, Training, & Certifications
- Ph.D., Purdue University 2004
Duke Appointment History
- Adjunct Associate Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2016
Recognition
In the News
- JAN 3, 2017
  
  Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain
Awards & Honors
Research
Selected Grants
- IUCRC Proposal Phase 1 Duke: Center for Alternative Sustainable and Intelligent Computing (ASIC) awarded by National Science Foundation 2018 - 2023
- IUCRC Proposal Phase 1 Duke: Center for Alternative Sustainable and Intelligent Computing (ASIC) awarded by National Science Foundation 2018 - 2023
- FET: Small:RESONANCE:Accelerating Speech/Language Processing through Collective Training using Commodity ReRAM Chips awarded by National Science Foundation 2019 - 2022
- SPX: Collaborative Research: Ula! - An Integrated DNN Acceleration Framework with Enhanced Unsupervised Learning Capability awarded by National Science Foundation 2017 - 2021
- The Controller Design and Integration of Memristor-based Neuromorphic System 2018 - 2021
- CSR: SMALL: Collaborative Research: GAMBIT: Efficient Graph Processing on a Memristor-based Embedded Computing Platform awarded by National Science Foundation 2017 - 2020
- Scalable Event-driven Neuromorphic Learning Mechanics for Human-centric Computing 2017 - 2020
- SMALE: Enhancing Scalability of Machine Learning Algorithms on Extreme Scale Computing Platforms awarded by Department of Energy 2017 - 2020
- Systematically Studying Backdoor Attacks on DNNs and Developing a Detection Architecture awarded by Army Research Office 2019
- SHF:Small: Cross-Platform Solutions for Pruning and Accelerating Neural Models awarded by National Science Foundation 2017 - 2019
- NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains awarded by National Science Foundation 2017 - 2018
- Planning IUCRC Duke University: Center for Alternative Sustainable and Intelligent Computing awarded by National Science Foundation 2017 - 2018
- The Design of Neuromorphic Controller System Built with Memristor Crossbars awarded by University of Pittsburgh 2017
Publications & Artistic Works
Selected Publications
- Books
  - Li, Hai, and Yiran Chen. Nonvolatile Memory Design Magnetic, Resistive, and Phase Change. CRC Press, 2011.
- Academic Articles
  - Yang, J., X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. “Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 38, no. 1 (January 1, 2019): 57–69. https://doi.org/10.1109/TCAD.2018.2802870.
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  - Wang, D., L. Ma, M. Zhang, J. An, H. H. Li, and Y. Chen. “Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.” Journal of Circuits, Systems and Computers 27, no. 5 (May 1, 2018). https://doi.org/10.1142/S0218126618500810.
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  - Zhang, L., W. Song, J. J. Yang, H. Li, and Y. Chen. “A compact model for selectors based on metal doped electrolyte.” Applied Physics A: Materials Science and Processing 124, no. 4 (April 1, 2018). https://doi.org/10.1007/s00339-018-1706-2.
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  - Basu, A., J. Acharya, T. Karnik, H. Liu, H. Li, J. S. Seo, and C. Song. “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 1 (March 1, 2018): 6–27. https://doi.org/10.1109/JETCAS.2018.2816339.
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  - Chen, Y., H. Li, C. Wu, C. Song, S. Li, C. Min, H. P. Cheng, W. Wen, and X. Liu. “Neuromorphic computing's yesterday, today, and tomorrow – an evolutional view.” Integration 61 (March 1, 2018): 49–61. https://doi.org/10.1016/j.vlsi.2017.11.001.
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  - Mohanty, S. P., M. Hüebner, C. J. Xue, X. Li, and H. Li. “Guest editorial circuit and system design automation for internet of things.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 1 (January 1, 2018): 3–6. https://doi.org/10.1109/TCAD.2017.2779960.
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  - Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.” Ieee Transactions on Computers 66, no. 9 (September 1, 2017): 1478–90. https://doi.org/10.1109/TC.2017.2690855.
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  - Hu, M., Y. Chen, J. J. Yang, Y. Wang, and H. Li. “A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (August 1, 2017): 1353–66. https://doi.org/10.1109/TCAD.2016.2618866.
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  - Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1167–80. https://doi.org/10.1109/TCAD.2016.2619480.
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  - Bi, X., M. Mao, D. Wang, and H. Li. “Cross-layer optimization for multilevel cell STT-RAM caches.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (June 1, 2017): 1807–20. https://doi.org/10.1109/TVLSI.2017.2665543.
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  - Chen, Y., H. H. Li, I. Bayram, and E. Eken. “Recent Technology Advances of Emerging Memories.” Ieee Design and Test 34, no. 3 (June 1, 2017): 8–22. https://doi.org/10.1109/MDAT.2017.2685381.
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  - Eken, E., I. Bayram, Y. Zhang, B. Yan, H. Li, and Y. Chen. “Giant Spin-Hall assisted STT-RAM and logic design.” Integration, the Vlsi Journal 58 (June 1, 2017): 253–61. https://doi.org/10.1016/j.vlsi.2017.04.002.
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  - Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” Ieee Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.
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  - Li, H. H., Y. Chen, C. Liu, J. P. Strachan, and N. Davila. “Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.” Ieee Consumer Electronics Magazine 6, no. 1 (January 1, 2017): 94–103. https://doi.org/10.1109/MCE.2016.2614523.
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  - Wu, Chunpeng, Hsin-Pai Cheng, Sicheng Li, Hai Helen Li, and Yiran Chen. “ApesNet: a pixel-wise efficient segmentation network for embedded devices.” Iet Cyber Physical Systems: Theory & Applications 1, no. 1 (December 1, 2016): 78–85. https://doi.org/10.1049/iet-cps.2016.0027.
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  - Li, H. H., Q. Qiu, and Y. Wang. “Guest Editorial: Design and Applications of Neuromorphic Computing System.” Ieee Transactions on Multi Scale Computing Systems 2, no. 4 (October 1, 2016): 223–24. https://doi.org/10.1109/TMSCS.2016.2631918.
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  - Qiu, Q., Z. Li, K. Ahmed, W. Liu, S. F. Habib, H. Li, and M. Hu. “A Neuromorphic Architecture for Context Aware Text Image Recognition.” Journal of Signal Processing Systems 84, no. 3 (September 1, 2016): 355–69. https://doi.org/10.1007/s11265-015-1067-4.
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  - Pyle, S. D., H. Li, and R. F. DeMara. “Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device.” Electronics Letters 52, no. 14 (July 7, 2016): 1238–40. https://doi.org/10.1049/el.2015.4114.
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  - Hu, M., Y. Wang, W. Wen, and H. Li. “Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 235–46. https://doi.org/10.1109/JETCAS.2016.2547780.
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  - Yang, J., Z. Sun, X. Wang, Y. Chen, and H. Li. “Spintronic Memristor as Interface between DNA and Solid State Devices.” Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 212–21. https://doi.org/10.1109/JETCAS.2016.2547700.
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  - Duan, S., Z. Dong, X. Hu, L. Wang, and H. Li. “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.” Neural Computing and Applications 27, no. 4 (May 1, 2016): 837–44. https://doi.org/10.1007/s00521-015-1899-7.
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  - Liu, X., M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, et al. “Harmonica: A Framework of Heterogeneous Computing Systems with Memristor-Based Neuromorphic Computing Accelerators.” Ieee Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 1, 2016): 617–28. https://doi.org/10.1109/TCSI.2016.2529279.
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  - Mao, F., Y. C. Chen, W. Zhang, H. Li, and B. He. “Library-based placement and routing in FPGAs with support of partial reconfiguration.” Acm Transactions on Design Automation of Electronic Systems 21, no. 4 (May 1, 2016). https://doi.org/10.1145/2901295.
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  - Sun, Z., X. Bi, W. Wu, S. Yoo, and H. H. Li. “Array Organization and Data Management Exploration in Racetrack Memory.” Ieee Transactions on Computers 65, no. 4 (April 1, 2016): 1041–54. https://doi.org/10.1109/TC.2014.2360545.
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  - Yang, J., P. Wang, Y. Zhang, Y. Cheng, W. Zhao, Y. Chen, and H. H. Li. “Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.” Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 3 (March 1, 2016): 380–93. https://doi.org/10.1109/TCAD.2015.2474366.
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  - Zhang, Y., Y. Li, Z. Sun, H. Li, Y. Chen, and A. K. Jones. “Read performance: The newest barrier in scaled stt-ram.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 23, no. 6 (June 1, 2015): 1170–74. https://doi.org/10.1109/TVLSI.2014.2326797.
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  - Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A novel self-reference technique for STT-RAM read and write reliability enhancement.” Ieee Transactions on Magnetics 50, no. 11 (November 1, 2014). https://doi.org/10.1109/TMAG.2014.2323196.
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  - Hu, Miao, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, and Richard W. Linderman. “Memristor crossbar-based neuromorphic computing system: a case study..” Ieee Transactions on Neural Networks and Learning Systems 25, no. 10 (October 2014): 1864–78. https://doi.org/10.1109/tnnls.2013.2296777.
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  - Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control..” Thescientificworldjournal 2014 (January 2014). https://doi.org/10.1155/2014/394828.
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  - Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.
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  - Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.
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  - Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” Acm Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.
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  - Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.” Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013). https://doi.org/10.1145/2500459.
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  - Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache.” Acm Transactions on Architecture and Code Optimization 10, no. 4 (January 1, 2013): 1–22. https://doi.org/10.1145/2541228.2555308.
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  - Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” Ieee Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.
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  - Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” Ieee Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.
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  - LI, H. A. I. H. E. L. E. N., and Z. H. E. N. Y. U. SUN. “VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT.” Spin 02, no. 03 (September 2012): 1240008–1240008. https://doi.org/10.1142/s2010324712400085.
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  - Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” Acm Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.
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  - Sun, Z., H. Li, and X. Wang. “Magnetic tunnel junction design margin exploration for self-reference sensing scheme..” Journal of Applied Physics 111, no. 7 (April 2012): 7C726–7263. https://doi.org/10.1063/1.3679647.
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  - Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme.” Ieee Journal of Solid State Circuits 47, no. 2 (February 1, 2012): 560–73. https://doi.org/10.1109/JSSC.2011.2170778.
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  - Sun, Z., H. Li, Y. Chen, and X. Wang. “Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (January 1, 2012): 2020–30. https://doi.org/10.1109/TVLSI.2011.2166282.
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  - Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of Inhibiting Amyloid Precursor Protein Processing Enzymes on Synaptic Function and Plasticity.” Neural Plasticity 2012 (2012): 1–24. https://doi.org/10.1155/2012/272374.
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  - Li, H., X. Wang, Z. L. Ong, W. F. Wong, Y. Zhang, P. Wang, and Y. Chen. “Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2356–59. https://doi.org/10.1109/TMAG.2011.2159262.
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  - Wang, P., X. Wang, Y. Zhang, H. Li, S. P. Levitan, and Y. Chen. “Nonpersistent errors optimization in spin-MOS logic and storage circuitry.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 3860–63. https://doi.org/10.1109/TMAG.2011.2153838.
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  - Zhang, Y., X. Wang, H. Li, and Y. Chen. “STT-RAM cell optimization considering MTJ and CMOS variations.” Ieee Transactions on Magnetics 47, no. 10 (October 1, 2011): 2962–65. https://doi.org/10.1109/TMAG.2011.2158810.
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  - Dong, X., X. Wu, Y. Xie, Y. Chen, and H. Li. “Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation.” Iet Computers and Digital Techniques 5, no. 3 (May 1, 2011): 213–20. https://doi.org/10.1049/iet-cdt.2009.0091.
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  - Hu, M., H. H. Li, Y. Chen, and X. Wang. “Spintronic memristor: Compact model and statistical analysis.” Journal of Low Power Electronics 7, no. 2 (April 1, 2011): 234–44. https://doi.org/10.1166/jolpe.2011.1131.
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  - Zhu, W., H. Li, Y. Chen, and X. Wang. “Current switching in MgO-based magnetic tunneling junctions.” Ieee Transactions on Magnetics 47, no. 1 PART 2 (January 1, 2011): 156–60. https://doi.org/10.1109/TMAG.2010.2085441.
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  - Chen, Y., X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. “Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (December 1, 2010): 1724–34. https://doi.org/10.1109/TVLSI.2009.2032192.
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  - Chen, Y., W. Tian, H. Li, X. Wang, and W. Zhu. “PCMO device with high switching stability.” Ieee Electron Device Letters 31, no. 8 (August 1, 2010): 866–68. https://doi.org/10.1109/LED.2010.2050457.
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  - Chen, Y., and H. Li. “Patents relevant to cross-point memory array.” Recent Patents on Electrical Engineering 3, no. 2 (June 25, 2010): 114–24. https://doi.org/10.2174/1874476111003020114.
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  - Xi, H., J. Stricklin, H. Li, Y. Chen, X. Wang, Y. Zheng, Z. Gao, and M. X. Tang. “Spin transfer torque memory with thermal assist mechanism: A case study.” Ieee Transactions on Magnetics 46, no. 3 PART 2 (March 1, 2010): 860–65. https://doi.org/10.1109/TMAG.2009.2033674.
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  - Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.
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  - Wang, X., Y. Chen, Y. Gu, and H. Li. “Spintronic memristor temperature sensor.” Ieee Electron Device Letters 31, no. 1 (January 1, 2010): 20–22. https://doi.org/10.1109/LED.2009.2035643.
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  - Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.
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  - Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.
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  - Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” Ieee Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.
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  - Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” Ieee Transactions on Magnetics 44, no. 11 PART 2 (November 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.
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  - Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.
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  - Li, H., S. Bhunia, Y. Chen, K. Roy, and T. N. Vijaykumar. “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design.” Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (March 1, 2004): 245–54. https://doi.org/10.1109/TVLSI.2004.824307.
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  - Agarwal, A., H. Li, and K. Roy. “A single-V t low-leakage gated-ground cache for deep submicron.” Ieee Journal of Solid State Circuits 38, no. 2 (February 1, 2003): 319–28. https://doi.org/10.1109/JSSC.2002.807414.
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  - Ablikim, M., M. N. Achasov, S. Ahmed, M. Albrecht, A. Amoroso, F. F. An, Q. An, et al. “Measurement of e+e−→π0π0ψ(3686) at s from 4.009 to 4.600 GeV and observation of a neutral charmoniumlike structure.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.052001.
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  - Ablikim, M., M. N. Achasov, S. Ahmed, O. Albayrak, M. Albrecht, M. Alekseev, D. J. Ambrose, et al. “Study of η(1475) and X(1835) in radiative J/ψ decays to γϕ.” Physical Review D 97, no. 5 (n.d.). https://doi.org/10.1103/physrevd.97.051101.
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- Book Sections
  - Li, Z., C. Liu, H. Li, and Y. Chen. “Neuromorphic hardware acceleration enabled by emerging technologies.” In Emerging Technology and Architecture for Big-Data Analytics, 217–44, 2017. https://doi.org/10.1007/978-3-319-54840-1_10.
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  - Chen, Y. C., Y. Wang, W. Zhang, Y. Chen, and H. H. Li. “In-place logic obfuscation for emerging nonvolatile FPGAs.” In Fundamentals of IP and SoC Security: Design, Verification, and Debug, 277–93, 2017. https://doi.org/10.1007/978-3-319-50057-7_11.
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  - Yang, C., H. Li, and Y. Chen. “Nanoscale memory architectures for neuromorphic computing.” In Security Opportunities in Nano Devices and Emerging Technologies, 215–34, 2017. https://doi.org/10.1201/9781315265056.
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  - Li, H. H., M. Hu, and B. Liu. “Memristor modeling - static, statistical, and stochastic methodologies.” In Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, 313–35, 2016. https://doi.org/10.1049/PBCS029E_ch11.
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  - Zhang, Y., W. Wen, H. Li, and Y. Chen. “The Prospect of STT-RAM Scaling.” In Metallic Spintronic Devices. CRC Press, 2014.
  - Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.
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  - Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.
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  - Chen, Y., H. Li, Y. Xie, and D. Niu. “Low Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing. CRC Press, 2012.
  - Li, H. H., M. Hu, and R. E. Pino. “Statistical memristor model and its applications in neuromorphic computing.” In Advances in Neuromorphic Memristor Science and Applications, 107–31, 2012. https://doi.org/10.1007/978-94-007-4491-2_8.
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  - Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.
- Conference Papers
  - Zhang, S., G. L. Zhang, B. Li, H. H. Li, and U. Schlichtmann. “Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.” In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, Date 2019, 1751–56, 2019. https://doi.org/10.23919/DATE.2019.8714954.
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  - Li, H. H., Y. Wang, and W. Wen. “Message from the technical program chairs.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:xiii–xiv, 2018. https://doi.org/10.1109/ISVLSI.2018.00006.
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  - Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, Y. Chen, and H. Li. “MAT: A multi-strength adversarial training method to mitigate adversarial attacks.” In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 2018-July:476–81, 2018. https://doi.org/10.1109/ISVLSI.2018.00092.
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  - Jiang, H., K. Yamada, Z. Ren, T. Kwok, F. Luo, Q. Yang, X. Zhang, et al. “Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.” In Proceedings Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351276.
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  - Yang, Q., H. Li, and Q. Wu. “A Quantized Training Method to Enhance Accuracy of ReRAM-based Neuromorphic Systems.” In Proceedings Ieee International Symposium on Circuits and Systems, Vol. 2018-May, 2018. https://doi.org/10.1109/ISCAS.2018.8351327.
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