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Unleashing the potential of MLC STT-RAM caches

Publication ,  Conference
Bi, X; Mao, M; Wang, D; Li, H
Published in: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
December 1, 2013

In this paper, we study the use of multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) in cache design of embedded systems and microprocessors. Compared to the single level cell (SLC) design, a MLC STT-RAM cache is expected to offer higher density and faster system performance. However, the cell design constrains, such as the switching current requirement and asymmetry in write operations, severely limit the density benefit of the conventional MLC STT-RAM. The two-step read/write accesses and inflexible data mapping strategy in the existing MLC STT-RAM cache architecture may even result in system performance degradation. To unleash the real potential of MLC STT-RAM cache, we propose a cross-layer solution. First, we introduce the reverse magnetic junction tunneling (MTJ) into MLC cell design, which offers a more balanced device and design tradeoff and enables 2x storage density than SLC. At architectural level, we propose a cell split mapping method to divide cache lines into fast and slow regions and data migration policies to allocate the frequently-used data to fast regions. Furthermore, an application-aware speed enhancement mode is utilized to adaptively tradeoff cache capacity and speed, satisfying different requirements of various applications. Simulation results show that the proposed techniques can improve the system performance by 10.3% and reduce the energy consumption on cache by 26.0% compared with conventional MLC STT-RAM. © 2013 IEEE.

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Published In

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

DOI

ISSN

1092-3152

ISBN

9781479910717

Publication Date

December 1, 2013

Start / End Page

429 / 436
 

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Bi, X., Mao, M., Wang, D., & Li, H. (2013). Unleashing the potential of MLC STT-RAM caches. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 429–436). https://doi.org/10.1109/ICCAD.2013.6691153
Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.
Bi X, Mao M, Wang D, Li H. Unleashing the potential of MLC STT-RAM caches. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2013. p. 429–36.
Bi, X., et al. “Unleashing the potential of MLC STT-RAM caches.” IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2013, pp. 429–36. Scopus, doi:10.1109/ICCAD.2013.6691153.
Bi X, Mao M, Wang D, Li H. Unleashing the potential of MLC STT-RAM caches. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2013. p. 429–436.

Published In

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

DOI

ISSN

1092-3152

ISBN

9781479910717

Publication Date

December 1, 2013

Start / End Page

429 / 436