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Data-Pattern-Aware Error Prevention Technique to Improve System Reliability

Publication ,  Journal Article
Guo, J; Wang, D; Shao, Z; Chen, Y
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
April 1, 2017
Published version (DOI)

Program disturb, read disturb, and retention time noise are identified as three major contributors to multilevel cell (MLC) NAND flash memory bit errors. With program/erase cycling and technology scaling, bit error rate (BER) of MLC NAND flash memory rapidly increases. Previous works revealed that BER is heavily dependent on data patterns. Based on this observation, we propose data-pattern-aware (DPA) error protection technique to extend the lifespan of NAND flash-based storage systems. DPA manipulates the ratios of 0's and 1's in the stored data to reduce the probability of the data patterns, which are susceptible to device noises. By minimizing the vulnerable data patterns, our scheme can effectively reduce the BER and improves the system endurance. Our DPA scheme also incorporates a data management scheme to minimize the redundancy-induced performance overhead. Simulation results show that our scheme can increase flash system life expectancy by up to 4 ×.

Duke Scholars

Yiran Chen
Author Yiran Chen Electrical and Computer Engineering
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Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

10.1109/TVLSI.2016.2642055

ISSN

1063-8210

Publication Date

April 1, 2017

Volume

25

Issue

4

Start / End Page

1433 / 1443

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing
 

Citation

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Guo, J., Wang, D., Shao, Z., & Chen, Y. (2017). Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1433–1443. https://doi.org/10.1109/TVLSI.2016.2642055
Guo, J., D. Wang, Z. Shao, and Y. Chen. “Data-Pattern-Aware Error Prevention Technique to Improve System Reliability.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (April 1, 2017): 1433–43. https://doi.org/10.1109/TVLSI.2016.2642055.
Guo J, Wang D, Shao Z, Chen Y. Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Apr 1;25(4):1433–43.
Guo, J., et al. “Data-Pattern-Aware Error Prevention Technique to Improve System Reliability.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, Apr. 2017, pp. 1433–43. Scopus, doi:10.1109/TVLSI.2016.2642055.
Guo J, Wang D, Shao Z, Chen Y. Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Apr 1;25(4):1433–1443.

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

10.1109/TVLSI.2016.2642055

ISSN

1063-8210

Publication Date

April 1, 2017

Volume

25

Issue

4

Start / End Page

1433 / 1443

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing