Statistical reliability/energy characterization in STT-RAM cell designs
Spin-transfer torque random access memory (STT-RAM) is a very promising candidate to replace the SRAM and DRAM based traditional memory systems. However, the development of STT-RAM is facing two major technical challenges—poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The evaluations on STT-RAM design metrics and robustness often require a hybrid simulation flow, i.e., modeling the CMOS and magnetic devices with SPICE and Macro-magnetic models, respectively. Very often, such a hybrid simulation flow involves expensive Monte-Carlo simulations when the design and behavioral variabilities of STT-RAM are taken into account. In this chapter, we will first analyze the prominent process variations and operation uncertainty in STT-RAM design. Then, a fast and scalable semi-analytical method—PS3-RAM will be introduced to enable efficient statistical simulations in STT-RAM designs, followed by its applications on modeling the STT-RAM cell write error rate and write energy distributions. The array-level reliability-driven design exploration of STT-RAM will be also discussed.
