Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units
Publication
, Conference
Xie, M; Pan, C; Hu, J; Yang, C; Chen, Y
Published in: 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
March 11, 2015
Embedded systems powered with harvested energy experience frequent execution interruption due to unstable energy source. Nonvolatile (NV) register based processor is proposed to realize fast resume after power failure. The states in the volatile registers are checkpointed to NV registers. However, frequent checkpointing causes performance degradation and consumes excessive power. In this paper, we propose the checkpoint aware instruction scheduling (CAIS) algorithm to reduce the writes to NV registers. Experiments show that CAIS can improve performance and reduce power consumption.
Duke Scholars
Published In
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
DOI
ISBN
9781479977925
Publication Date
March 11, 2015
Start / End Page
316 / 321
Citation
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Chicago
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Xie, M., Pan, C., Hu, J., Yang, C., & Chen, Y. (2015). Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 316–321). https://doi.org/10.1109/ASPDAC.2015.7059024
Xie, M., C. Pan, J. Hu, C. Yang, and Y. Chen. “Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.” In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, 316–21, 2015. https://doi.org/10.1109/ASPDAC.2015.7059024.
Xie M, Pan C, Hu J, Yang C, Chen Y. Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units. In: 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. 2015. p. 316–21.
Xie, M., et al. “Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.” 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, 2015, pp. 316–21. Scopus, doi:10.1109/ASPDAC.2015.7059024.
Xie M, Pan C, Hu J, Yang C, Chen Y. Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. 2015. p. 316–321.
Published In
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
DOI
ISBN
9781479977925
Publication Date
March 11, 2015
Start / End Page
316 / 321