STT-RAM reliability enhancement through ECC and access scheme optimization
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Wen, W; Zhang, Y; Mao, M; Chen, Y
Published in: Proceedings of the International Symposium on Consumer Electronics, ISCE
January 1, 2014
Multi-level cell Spin-Transfer Torque RAM (MLC STT-RAM) greatly suffers from the significantly degraded operation reliability and high programming cost. In this paper, a novel MLC design, namely ternary-state MLC (TS-MLC STT-RAM), is proposed for high-reliable high-performance memory systems by leveraging a cross-layer solution set. Based on the structure, several circuit and architecture schemes are proposed to enhance both the reliability and access latency of the memory cells. © 2014 IEEE.
Duke Scholars
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Proceedings of the International Symposium on Consumer Electronics, ISCE
DOI
Publication Date
January 1, 2014
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Wen, W., Zhang, Y., Mao, M., & Chen, Y. (2014). STT-RAM reliability enhancement through ECC and access scheme optimization. In Proceedings of the International Symposium on Consumer Electronics, ISCE. https://doi.org/10.1109/ISCE.2014.6884324
Wen, W., Y. Zhang, M. Mao, and Y. Chen. “STT-RAM reliability enhancement through ECC and access scheme optimization.” In Proceedings of the International Symposium on Consumer Electronics, ISCE, 2014. https://doi.org/10.1109/ISCE.2014.6884324.
Wen W, Zhang Y, Mao M, Chen Y. STT-RAM reliability enhancement through ECC and access scheme optimization. In: Proceedings of the International Symposium on Consumer Electronics, ISCE. 2014.
Wen, W., et al. “STT-RAM reliability enhancement through ECC and access scheme optimization.” Proceedings of the International Symposium on Consumer Electronics, ISCE, 2014. Scopus, doi:10.1109/ISCE.2014.6884324.
Wen W, Zhang Y, Mao M, Chen Y. STT-RAM reliability enhancement through ECC and access scheme optimization. Proceedings of the International Symposium on Consumer Electronics, ISCE. 2014.
Published In
Proceedings of the International Symposium on Consumer Electronics, ISCE
DOI
Publication Date
January 1, 2014