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STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures

Publication ,  Conference
Liu, X; Li, Y; Zhang, Y; Jones, AK; Chen, Y
Published in: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
March 27, 2014

Translation lookaside buffer (TLB) was recently introduced into modern graphics processing unit (GPU) architectures to support virtual memory addressing. Compared to CPUs, the performance of GPUs is more sensitive to the capacity of TLBs because of heavier memory accesses. However, large SRAM cell area greatly limits the implementable capacity of conventional SRAM-based TLBs. In this work, we propose using STT-RAM to construct TLBs in light of the unique memory access pattern in GPUs, i.e., infrequent data updates. STT-RAM TLB can replace its same-area SRAM counterpart with greater capacity, similar read performance and lower energy consumption. As an optimization of STT-RAM TLB, we further propose a STT-RAM-based dynamically-configurable TLB (STD-TLB) by leveraging differential sensing technique. STD-TLB can switch between high-capacity mode and high-performance mode on-the-fly based on real-time application needs. Our experiments show that compared to SRAM TLB, standard STT-RAM TLB improves the performance and energy delay product of GPU address translation by 32% and 75%, respectively, while STD-TLB achieves additional 15% and 13% improvements over standard STT-RAM TLB. © 2014 IEEE.

Duke Scholars

Published In

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

DOI

Publication Date

March 27, 2014

Start / End Page

355 / 360
 

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Liu, X., Li, Y., Zhang, Y., Jones, A. K., & Chen, Y. (2014). STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 355–360). https://doi.org/10.1109/ASPDAC.2014.6742915
Liu, X., Y. Li, Y. Zhang, A. K. Jones, and Y. Chen. “STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 355–60, 2014. https://doi.org/10.1109/ASPDAC.2014.6742915.
Liu X, Li Y, Zhang Y, Jones AK, Chen Y. STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 355–60.
Liu, X., et al. “STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.” Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2014, pp. 355–60. Scopus, doi:10.1109/ASPDAC.2014.6742915.
Liu X, Li Y, Zhang Y, Jones AK, Chen Y. STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 355–360.

Published In

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

DOI

Publication Date

March 27, 2014

Start / End Page

355 / 360