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Cache coherence enabled adaptive refresh for volatile STT-RAM

Publication ,  Conference
Li, J; Shi, L; Li, Q; Xue, CJ; Chen, Y; Xu, Y
Published in: Proceedings -Design, Automation and Test in Europe, DATE
January 1, 2013

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead. © 2013 EDAA.

Duke Scholars

Published In

Proceedings -Design, Automation and Test in Europe, DATE

DOI

ISSN

1530-1591

Publication Date

January 1, 2013

Start / End Page

1247 / 1250
 

Citation

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Li, J., Shi, L., Li, Q., Xue, C. J., Chen, Y., & Xu, Y. (2013). Cache coherence enabled adaptive refresh for volatile STT-RAM. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 1247–1250). https://doi.org/10.7873/date.2013.258
Li, J., L. Shi, Q. Li, C. J. Xue, Y. Chen, and Y. Xu. “Cache coherence enabled adaptive refresh for volatile STT-RAM.” In Proceedings -Design, Automation and Test in Europe, DATE, 1247–50, 2013. https://doi.org/10.7873/date.2013.258.
Li J, Shi L, Li Q, Xue CJ, Chen Y, Xu Y. Cache coherence enabled adaptive refresh for volatile STT-RAM. In: Proceedings -Design, Automation and Test in Europe, DATE. 2013. p. 1247–50.
Li, J., et al. “Cache coherence enabled adaptive refresh for volatile STT-RAM.” Proceedings -Design, Automation and Test in Europe, DATE, 2013, pp. 1247–50. Scopus, doi:10.7873/date.2013.258.
Li J, Shi L, Li Q, Xue CJ, Chen Y, Xu Y. Cache coherence enabled adaptive refresh for volatile STT-RAM. Proceedings -Design, Automation and Test in Europe, DATE. 2013. p. 1247–1250.

Published In

Proceedings -Design, Automation and Test in Europe, DATE

DOI

ISSN

1530-1591

Publication Date

January 1, 2013

Start / End Page

1247 / 1250