Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors
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, Conference
Chen, Y; Roy, K; Koh, CK
Published in: Proceedings of the International Symposium on Low Power Electronics and Design
January 1, 2003
We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, the decoupling capacitance requirement by 21.8%. The degradation in IPC (instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18 μm technology.
Duke Scholars
Published In
Proceedings of the International Symposium on Low Power Electronics and Design
DOI
ISSN
1533-4678
Publication Date
January 1, 2003
Volume
2003-January
Start / End Page
229 / 234
Citation
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Chen, Y., Roy, K., & Koh, C. K. (2003). Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In Proceedings of the International Symposium on Low Power Electronics and Design (Vol. 2003-January, pp. 229–234). https://doi.org/10.1109/LPE.2003.1231867
Chen, Y., K. Roy, and C. K. Koh. “Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.” In Proceedings of the International Symposium on Low Power Electronics and Design, 2003-January:229–34, 2003. https://doi.org/10.1109/LPE.2003.1231867.
Chen Y, Roy K, Koh CK. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229–34.
Chen, Y., et al. “Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.” Proceedings of the International Symposium on Low Power Electronics and Design, vol. 2003-January, 2003, pp. 229–34. Scopus, doi:10.1109/LPE.2003.1231867.
Chen Y, Roy K, Koh CK. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229–234.
Published In
Proceedings of the International Symposium on Low Power Electronics and Design
DOI
ISSN
1533-4678
Publication Date
January 1, 2003
Volume
2003-January
Start / End Page
229 / 234