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Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

Publication ,  Conference
Chen, Y; Roy, K; Koh, CK
Published in: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
June 1, 2004

We propose an integrated architectural/physical-planning approach named priority assignment optimization to minimize the current surge in high performance power efficient clock-gated microprocessors. The proposed approach balances the current demands across the floorplan by assigning optimized priorities to the functional units (FUs). Two complementary methods - physical planning with soft modules and issue pattern management - to enhance our proposed approach are also discussed for various applications. Experimental results show that the proposed approach reduces the peak noise by 11.75% and consequently, the decoupling capacitance (Decap) requirement by 24.22% without any degradation in IPC (Instruction Per Cycle). We also show that our approach does not increase the clock period for the 0.18μm technology and beyond.

Duke Scholars

Published In

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Publication Date

June 1, 2004

Start / End Page

894 / 899
 

Citation

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Chen, Y., Roy, K., & Koh, C. K. (2004). Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 894–899).
Chen, Y., K. Roy, and C. K. Koh. “Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 894–99, 2004.
Chen Y, Roy K, Koh CK. Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 894–9.
Chen, Y., et al. “Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.” Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2004, pp. 894–99.
Chen Y, Roy K, Koh CK. Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 894–899.

Published In

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Publication Date

June 1, 2004

Start / End Page

894 / 899