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Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories

Publication ,  Journal Article
Kim, Y; Kim, J; Kong, JJ; Vijaya Kumar, BVK; Li, X
Published in: Eurasip Journal on Advances in Signal Processing
December 1, 2012

In 1 M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell. © 2012 Kim et al.; licensee Springer.

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Published In

Eurasip Journal on Advances in Signal Processing

DOI

EISSN

1687-6180

ISSN

1687-6172

Publication Date

December 1, 2012

Volume

2012

Issue

1

Related Subject Headings

  • Networking & Telecommunications
  • 4603 Computer vision and multimedia computation
  • 4006 Communications engineering
  • 0906 Electrical and Electronic Engineering
  • 0801 Artificial Intelligence and Image Processing
 

Citation

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Kim, Y., Kim, J., Kong, J. J., Vijaya Kumar, B. V. K., & Li, X. (2012). Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories. Eurasip Journal on Advances in Signal Processing, 2012(1). https://doi.org/10.1186/1687-6180-2012-196
Kim, Y., J. Kim, J. J. Kong, B. V. K. Vijaya Kumar, and X. Li. “Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories.” Eurasip Journal on Advances in Signal Processing 2012, no. 1 (December 1, 2012). https://doi.org/10.1186/1687-6180-2012-196.
Kim Y, Kim J, Kong JJ, Vijaya Kumar BVK, Li X. Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories. Eurasip Journal on Advances in Signal Processing. 2012 Dec 1;2012(1).
Kim, Y., et al. “Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories.” Eurasip Journal on Advances in Signal Processing, vol. 2012, no. 1, Dec. 2012. Scopus, doi:10.1186/1687-6180-2012-196.
Kim Y, Kim J, Kong JJ, Vijaya Kumar BVK, Li X. Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories. Eurasip Journal on Advances in Signal Processing. 2012 Dec 1;2012(1).
Journal cover image

Published In

Eurasip Journal on Advances in Signal Processing

DOI

EISSN

1687-6180

ISSN

1687-6172

Publication Date

December 1, 2012

Volume

2012

Issue

1

Related Subject Headings

  • Networking & Telecommunications
  • 4603 Computer vision and multimedia computation
  • 4006 Communications engineering
  • 0906 Electrical and Electronic Engineering
  • 0801 Artificial Intelligence and Image Processing