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Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning

Publication ,  Journal Article
Alawieh, MB; Wang, F; Li, X
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
December 1, 2018

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.6 × runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

Duke Scholars

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

December 1, 2018

Volume

37

Issue

12

Start / End Page

2986 / 2998

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

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Chicago
ICMJE
MLA
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Alawieh, M. B., Wang, F., & Li, X. (2018). Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(12), 2986–2998. https://doi.org/10.1109/TCAD.2018.2789778
Alawieh, M. B., F. Wang, and X. Li. “Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 12 (December 1, 2018): 2986–98. https://doi.org/10.1109/TCAD.2018.2789778.
Alawieh MB, Wang F, Li X. Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018 Dec 1;37(12):2986–98.
Alawieh, M. B., et al. “Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, Dec. 2018, pp. 2986–98. Scopus, doi:10.1109/TCAD.2018.2789778.
Alawieh MB, Wang F, Li X. Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018 Dec 1;37(12):2986–2998.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

December 1, 2018

Volume

37

Issue

12

Start / End Page

2986 / 2998

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering