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Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation

Publication ,  Journal Article
Tao, J; Su, Y; Zhou, D; Zeng, X; Li, X
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
August 1, 2019
Published version (DOI)

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.

Duke Scholars

Xin Li
Author Xin Li Electrical and Computer Engineering

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

10.1109/TCAD.2018.2848590

EISSN

1937-4151

ISSN

0278-0070

Publication Date

August 1, 2019

Volume

38

Issue

8

Start / End Page

1385 / 1398

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
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Tao, J., Su, Y., Zhou, D., Zeng, X., & Li, X. (2019). Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(8), 1385–1398. https://doi.org/10.1109/TCAD.2018.2848590
Tao, J., Y. Su, D. Zhou, X. Zeng, and X. Li. “Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 8 (August 1, 2019): 1385–98. https://doi.org/10.1109/TCAD.2018.2848590.
Tao J, Su Y, Zhou D, Zeng X, Li X. Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 Aug 1;38(8):1385–98.
Tao, J., et al. “Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 8, Aug. 2019, pp. 1385–98. Scopus, doi:10.1109/TCAD.2018.2848590.
Tao J, Su Y, Zhou D, Zeng X, Li X. Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 Aug 1;38(8):1385–1398.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

10.1109/TCAD.2018.2848590

EISSN

1937-4151

ISSN

0278-0070

Publication Date

August 1, 2019

Volume

38

Issue

8

Start / End Page

1385 / 1398

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering