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Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory

Publication ,  Journal Article
Wang, C; Feng, D; Tong, W; Hua, Y; Liu, J; Wu, B; Zhao, W; Song, L; Zhang, Y; Xu, J; Wei, X; Chen, Y
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
April 1, 2021

Resistive memory is promising to be constructed as a high-density storage-class memory. Multilevel cell, access-transistor-free cross-point array structure, and 3-D array integration are three approaches to scale up the density of resistive memory. However, composing the three approaches together strengthens the interactions between array-level and cell-level nonidealities (interconnect resistance-induced IR drop, sneak current, and device variability) of resistive memory arrays during write operations and significantly degrades write performance and reliability. In this article, we analyze the dynamic voltage-dividing effect along a selected write current path in 3-D cross-point memory arrays. We propose a nonideality-tolerant high-density resistive memory (HD-RRAM) architecture, that can weaken the interactions between nonidealities and mitigate their degradation effects on the performance and reliability of array multilevel write operations. HD-RRAM is equipped with a double-transistor array architecture with two-transistor-$n$-resistor (2TnR) cell organization along pillars to reduce the current driving requirement and the large undesired voltage drop across each vertical pillar access transistor. Moreover, multiside asymmetric bias improves the resistive switching velocity by leveraging current-dividing effects. Variability-aware multilevel state partition reduces the worst-case write error rate by leveraging target state dependency of variability. Proportional-control multilevel state tuning reduces the average number of required write-and-verify iterations by leveraging pulse amplitude dependency of variability. Multilevel cell parallel writing improves the cell-level parallelism by leveraging the pass-through feature of intermediate resistance states. The evaluations show that HD-RRAM reduces both memory access latency and energy consumption over an aggressive baseline.

Duke Scholars

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

EISSN

1937-4151

ISSN

0278-0070

Publication Date

April 1, 2021

Volume

40

Issue

4

Start / End Page

762 / 775

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
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Wang, C., Feng, D., Tong, W., Hua, Y., Liu, J., Wu, B., … Chen, Y. (2021). Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(4), 762–775. https://doi.org/10.1109/TCAD.2020.3006188
Wang, C., D. Feng, W. Tong, Y. Hua, J. Liu, B. Wu, W. Zhao, et al. “Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40, no. 4 (April 1, 2021): 762–75. https://doi.org/10.1109/TCAD.2020.3006188.
Wang C, Feng D, Tong W, Hua Y, Liu J, Wu B, et al. Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2021 Apr 1;40(4):762–75.
Wang, C., et al. “Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, Apr. 2021, pp. 762–75. Scopus, doi:10.1109/TCAD.2020.3006188.
Wang C, Feng D, Tong W, Hua Y, Liu J, Wu B, Zhao W, Song L, Zhang Y, Xu J, Wei X, Chen Y. Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2021 Apr 1;40(4):762–775.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

EISSN

1937-4151

ISSN

0278-0070

Publication Date

April 1, 2021

Volume

40

Issue

4

Start / End Page

762 / 775

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering