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Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction

Publication ,  Journal Article
Wang, C; Feng, D; Tong, W; Liu, J; Wu, B; Chen, Y
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
October 1, 2022

Three-dimensional (3-D) integrated cross-point memory arrays can be used to build high-density storage-class memory systems. However, the coupled network topology caused by sharing word lines or bit lines between adjacent memory layers significantly enlarges the memory space overhead and time cost of memory operation simulations on mega-scale 3-D cross-point memory arrays. We observe that different components of the 3-D cross-point array have different contribution significance to the key metrics of write or read operations, and the distribution patterns of principal components in the arrays are different for write and read operations. We propose an operation-adaptive array modeling framework that exploits the impact of the applied operation on the distribution of array principal components for 3-D cross-point memory arrays. Based on the modeling framework, we propose two array network compaction methods for efficient write and read operation simulations on 3-D cross-point arrays, respectively: 1) pruning zero-biased unselected cells and 2) group-merging neighboring half-selected cells with a specific granularity. Also, serially connected line segments are merged, and floating segments are deleted. Evaluations show that the proposed methods significantly reduce the memory space overhead and time cost of memory operation simulations for various layer sizes and different cell-level access parallelism in an array. Besides, the proposed methods can efficiently simulate memory operations on multilayered 3-D cross-point memory arrays with up to 4096× 4096 layer size under the 16-GB memory space constraint, achieving a 64-times improvement in layer size that can be simulated compared with the conventional complete 3-D cross-point array network model.

Duke Scholars

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

EISSN

1937-4151

ISSN

0278-0070

Publication Date

October 1, 2022

Volume

41

Issue

10

Start / End Page

3479 / 3491

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
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Wang, C., Feng, D., Tong, W., Liu, J., Wu, B., & Chen, Y. (2022). Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10), 3479–3491. https://doi.org/10.1109/TCAD.2021.3123591
Wang, C., D. Feng, W. Tong, J. Liu, B. Wu, and Y. Chen. “Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41, no. 10 (October 1, 2022): 3479–91. https://doi.org/10.1109/TCAD.2021.3123591.
Wang C, Feng D, Tong W, Liu J, Wu B, Chen Y. Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022 Oct 1;41(10):3479–91.
Wang, C., et al. “Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, Oct. 2022, pp. 3479–91. Scopus, doi:10.1109/TCAD.2021.3123591.
Wang C, Feng D, Tong W, Liu J, Wu B, Chen Y. Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022 Oct 1;41(10):3479–3491.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

EISSN

1937-4151

ISSN

0278-0070

Publication Date

October 1, 2022

Volume

41

Issue

10

Start / End Page

3479 / 3491

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering