A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
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Yan, B; Hsu, JL; Yu, PC; Lee, CC; Zhang, Y; Yue, W; Mei, G; Yang, Y; Li, H; Chen, Y; Huang, R
Published in: Digest of Technical Papers - IEEE International Solid-State Circuits Conference
January 1, 2022
Advanced intelligent embedded systems perform cognitive tasks with highly-efficient vector-processing units for deep neural network (DNN) inference and other vector-based signal processing using limited power. SRAM-based compute-in-memory (CIM) achieves high energy efficiency for vector-matrix multiplications, offers <1ns read/write speed, and saves vastly repeating memory accesses. However, prior SRAM CIM macros require a large area for compute circuits (either using ADC for analog CIM [1- 4] or CMOS static logic for all-digital CIM [5-6]), have limited CIM functions, and use fixed vector-processing dimensions that cause a low-spatial-utilization rate when deploying DNN (Fig. 11.7.1).
Duke Scholars
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Digest of Technical Papers - IEEE International Solid-State Circuits Conference
DOI
ISSN
0193-6530
Publication Date
January 1, 2022
Volume
2022-February
Start / End Page
188 / 190
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Yan, B., Hsu, J. L., Yu, P. C., Lee, C. C., Zhang, Y., Yue, W., … Huang, R. (2022). A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 2022-February, pp. 188–190). https://doi.org/10.1109/ISSCC42614.2022.9731545
Yan, B., J. L. Hsu, P. C. Yu, C. C. Lee, Y. Zhang, W. Yue, G. Mei, et al. “A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.” In Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2022-February:188–90, 2022. https://doi.org/10.1109/ISSCC42614.2022.9731545.
Yan B, Hsu JL, Yu PC, Lee CC, Zhang Y, Yue W, et al. A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2022. p. 188–90.
Yan, B., et al. “A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.” Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2022-February, 2022, pp. 188–90. Scopus, doi:10.1109/ISSCC42614.2022.9731545.
Yan B, Hsu JL, Yu PC, Lee CC, Zhang Y, Yue W, Mei G, Yang Y, Li H, Chen Y, Huang R. A 1.041-Mb/mm227.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2022. p. 188–190.
Published In
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
DOI
ISSN
0193-6530
Publication Date
January 1, 2022
Volume
2022-February
Start / End Page
188 / 190