Deep Learning for Routability
Design rule checking (DRC) clean is a fundamental chip manufacturing requirement. However, achieving this is increasingly challenging with the advance of semiconductor technology nodes and the increase of complicated design rules. To effectively mitigate DRC violations, early routability predictions are adopted in chip design flows for designers or tools to prevent violations in a proactive manner. In recent years, machine learning, especially deep learning (DL)-based routability estimators, have demonstrated their great potential in providing fast yet accurate predictions in early design stages. This chapter introduces representative and state-of-the-art DL-based methods for routability prediction in detail. After presenting the background on routability and relevant DL techniques, we emphasize the importance of global information and model receptive field, which motivates the adoption of DL models for routability predictions. After that, methodologies about data generation, feature engineering, model architecture design, and model construction are introduced. Finally, we cover existing explorations in the deployment of routability estimators and then summarize and share our point of view on the future of DL for routability prediction.
